Electrode and method of forming the electrode

ABSTRACT

An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier ( 1 ) provided with an insulating layer ( 7 ) which is patterned at a front side. Conducting material in an electrode layer ( 4 ) is applied in the cavities of the patterned insulating layer and in contact with the carrier. An connection layer ( 5 ) is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.

AREA OF INVENTION

The present invention relates to a master electrode and a method offorming the master electrode. The master electrode is useable in anetching or plating method as described in a copending Swedish patentapplication No. 0502538-2 filed concurrently herewith and entitled“METHOD OF FORMING A MULTILAYER STRUCTURE” (attorney reference:P52190002). The content of this patent specification is incorporatedherein by reference. The master electrode is suitable for enablingproduction of applications involving micro and nano structures in singleor multiple layers. The master electrode is useful for fabrication ofPWB (printed wiring boards), PCB (printed circuit boards), MEMS (microelectro mechanical systems), IC (integrated circuit) interconnects,above IC interconnects, sensors, flat panel displays, magnetic andoptical storage devices, solar cells and other electronic devices.Different types of structures in conductive polymers, structures insemiconductors, structures in metals, and others are possible to produceusing this master electrode. Even 3D-structures in silicon, such as byusing formation of porous silicon, are possible to produce.

BACKGROUND ART

WO 02/103085 relates to an electrochemical pattern replication method,ECPR, and a construction of a conductive master electrode for productionof appliances involving micro and nano structures. An etching or platingpattern, which is defined by a master electrode, is replicated on anelectrically conductive material, a substrate. The master electrode isput in close contact with the substrate and the etching/plating patternis directly transferred onto the substrate by using a contactetching/plating process. The contact etching/plating process isperformed in local etching/plating cells, which are formed in closed oropen cavities between the master electrode and the substrate.

The master electrode is used for cooperation with a substrate, ontowhich a structure is to be built. The master electrode forms at leastone, normally a plurality of electrochemical cells in which etching orplating takes place.

The master electrode may be made of a durable material, since the masterelectrode should be used for a plurality of processes of etching orplating.

A problem is that the master electrode is to be arranged in a carefullyadjusted position on the substrate in order for the pattern to bealigned with previous structures on the substrate.

A further problem is that the master electrode is to be arranged inclose proximity of a substrate when said substrate comprises topography.

A yet further problem is that the etching rate or plating rate may behigher in the electrochemical cells located closer to the contact areaof the seed layer, such as in the perimeter, than in other areas.

Further problems are mentioned below.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an electrode in whichthe above-mentioned problems are at least partly eliminated oralleviated.

Another object is to provide a master electrode that can be used forseveral processes of etching or plating.

A further object is to provide a master electrode that may be adjustedin relation to a previous structure on a substrate.

A further object is to provide a master electrode that enables improvedetching or plating rate uniformity in the electrochemical cellsindependent of where the cells are located with respect to the contactarea of the seed layer.

A further object is to provide a master electrode that can be arrangedin close proximity of a substrate, which comprises topography.

According to an aspect of the invention, there is provided a method offorming a master electrode, comprising: providing a disc having a frontsurface and a back surface being of a conducting or semiconductingmaterial; forming an insulating coating layer circumscribing at least apart of the disc; forming a conducting electrode layer of an electrodeforming, conducting material on at least a part of the front surface,said conducting electrode layer being in electrical connection with saiddisc via at least one opening in the insulating coating layer; formingan insulating pattern layer comprising at least one cavity on saidconducting electrode layer. The method may further comprise: forming acontact layer of a conducting material on at least a part of the backsurface, said contact layer being in electrical connection with saiddisc via at least one opening in the insulating coating layer.

In another aspect, there is provided a method of forming a masterelectrode, comprising: providing a insulating disc having a frontsurface and a back surface and being of an insulating material; forminga connection via in said insulating disc of a conducting material;forming an electrode layer of a conducting material on at least a partof the front surface, said electrode layer being in electricalconnection with said via; forming an insulating pattern layer comprisingat least one cavity on said electrode layer. The method may furthercomprise: forming a contact layer of a conducting material on at least apart of the back surface, said contact layer being in electricalconnection with said via.

In a further aspect, there is provided a method of forming a masterelectrode, comprising: providing a disc of at least one layer of aconducting and/or semi-conducting material; forming an insulating layerat least partly of at least one layer of an insulating material; formingat least one recesses in said insulating material; forming a conductingelectrode layer of an electrode forming, conducting material in eachrecess; and forming at least one recess at the back side of saidinsulating layer. The method may further comprise: forming a connectionlayer of at least one layer of a conducting and/or semi-conductingmaterial in electrical contact with said disc and said electrode layerat the back side of said insulating layer. The method may furthercomprise: applying at least another conducting layer.

In yet an aspect, there is provided a method of forming a masterelectrode, comprising: providing a carrier of at least one layer of aconducting and/or semi-conducting material; providing several recessesin said layer of a conducting and/or semi-conducting material; providingat least one layer of an insulating layer between the recesses. Themethod may further comprise: providing at least one layer of aconducting electrode layer at a bottom surface of said at least onerecess. The method may further comprise: providing at least one layer ofan insulating material at a back side of said carrier; and providing atleast one recess in said insulating material forming a connection. Themethod may further comprise: providing at least one conducting electrodelayer is said recess of the insulating material. The method may furthercomprise: providing at least one layer of an insulating material at sidesurfaces of said at least one recess. The method may further comprise:applying insulating material covering substantially all surfaces of thefront-side of the carrier; and removing the insulating material fromsaid bottom surfaces of the recesses in the carrier.

The insulated material may be applied by a method selected from thegroup comprising: thermal oxidation, thermal nitridation, sputtering,PECVD and ALD. The insulated material may be removed by anisotropicetching, such as dry-etching, having a higher etch rate in a directionnormal to said bottom surfaces than in a direction normal to said sidesurfaces of the recesses. The insulated material may be removed from thebottom surfaces of the recesses by lithography and etching.

In an embodiment, the method may further comprise: forming said at leastone recess in said carrier by using said insulating material layer as anetch-mask. At least one layer of a further insulating material may bearranged above said insulating layer.

In a still other aspect, there is provided a master electrode forforming an electrochemical cell with a substrate, comprising: a carrierat least partly of a conducting material; an insulating pattern layer atleast partly of at least one layer of an insulating material andarranged substantially at a front surface of said carrier and comprisingat least one cavity; wherein said carrier comprises: a disc of a atleast one layer of conducting or semi-conducting material provided withan insulating coating layer; and at least one conducing electrode layerof an electrode forming material and at least partly covering a frontsurface of the disc and being in electric contact with said disc. Thecarrier may comprise: a connection portion of at least one layer of aconducting material and covering at least a portion of the backsidesurface of the disc and/or being in electric contact with said disc andsaid electrode layer. The insulating coating layer may cover all partsof conducting or semiconducting material in said disc except for in thecenter parts of the backside and the front-side of said disc. Theinsulating coating layer may selectively cover specific parts of saiddisc or covers substantially all of the conducting or semiconductinglayers of said disc and wherein parts of the insulating material coatingis removed in selected areas, for instance by etching methods, such aswet-etching or dry-etching methods; or by mechanical abrasive methods.

In a still another aspect, there is provided a master electrode forforming an electrochemical cell with a substrate, comprising: a carrierat least partly of at least one layer of a conducting and/orsemi-conducting material; an insulating pattern layer at least partly ofat least one layer of an insulating material and arranged substantiallyat a front surface of said carrier; wherein said carrier comprises: adisc of at least one layer of an insulating material, which is possiblytransparent; an conducting electrode layer of at least one layer of anelectrode forming material and covering at least a part of a frontsurface of the disc; a via layer of at least one layer of a conductingmaterial and being in electrical contact with said electrode layer. Aconnection layer may be in electric contact with said via layer andelectrode layer. The connection layer may comprise at least one layer ofa conducting material covering at least a portion of a backside surfaceof the disc. The disc may comprise at least one layer of an insulatingmaterial, which is possibly transparent, in which at least some parts ofthe disc comprises a conducting or semiconducting material. Theconducting or semiconducting parts may be applied in the center of saidinsulating disc.

In a yet other aspect, there is provided a master electrode for formingan electrochemical cell with a substrate, comprising: a disc of at leastone layer of a conducting and/or semi-conducting material; an insulatinglayer at least partly of at least one layer of an insulating material;said insulating pattern layer at a front side thereof being providedwith at least one recess, each being provided with a conductingelectrode layer of an electrode forming, conducting material; saidinsulating layer at a back side being provided with at least one recess.The insulating layer may be arranged substantially surrounding saiddisc. The recess on the back side of said insulating layer may beprovided with a connection layer comprised of at least one layer of aconducting and/or semi-conducting material being in electrical contactwith said disc and said electrode layer. The master electrode mayfurther comprise at least another conducting layer.

In a yet another aspect, there is provided a master electrode forforming an electrochemical cell with a substrate, comprising: a carrierof at least one layer of a conducting and/or semi-conducting material,said carrier at a front side being provided with several recesses and atleast one layer of an insulating layer being arranged between therecesses. Each recess in said at least one layer of a conducting and/orsemi-conducting material may comprise a bottom surface and sidesurfaces, and said side surfaces being provided with at least one layerof an insulating material. The bottom surface may be provided with atleast one layer of a conducting electrode layer of an electrode forming,conducting material.

In an embodiment, the carrier may be made from at least one layer of aconducting and/or semi-conducting material and may be provided with anconducting electrode layer of a electrode forming, conducting materialin cavities of said insulating pattern layer. The carrier may be madefrom at least one layer of a conducting and/or semi-conducting material;recesses being provided in said front surface for forming a pattern,wherein insulating material is arranged covering the areas between therecesses and wherein conducting electrode layer (4) is arranged in thebottom surfaces of said recesses.

In an embodiment, the master electrode may be provided with recesses forarranging contacts for the substrate. Contacts means may be arranged forengagement with a substrate surface when the electrode is applied tosaid substrate for forming electrical contact with said substratesurface. The contact means may be arranged at the peripheral surface ofthe carrier outside said insulating material.

In an embodiment, the disc may be made from an elastic and/or flexiblematerial. The front surface of the insulating pattern layer may beprovided with formations corresponding to a three-dimensional structureof a substrate to be contacted.

In an embodiment, the sidewalls of the cavities of the insulatingpattern layer may be arranged with an inclination in relation to thenormal to the front surface.

In an embodiment, an anode material is predeposited in cavities of theinsulating pattern layer in contact with said conducting electrodelayer. The anode material may be predeposited with a method selectedfrom the group comprising: electroplating, electroless plating,immersion plating, CVD, MOCVD, (charged) powder-coating, chemicalgrafting, electrografting, and combinations thereof. The method fordepositing said anode material may be electroplating or electrolessplating.

In an embodiment, the layers of said carrier may be flexible forcompensating for waviness or unevenness of a substrate, for giving acontact between said insulating pattern layer and said substratesurface, when the master electrode is pressed against the substrate. Thelayers of said carrier may be rigid for avoiding bending down into thecavities of said insulating pattern layer when applying a force forputting said master electrode in contact with a substrate. The bendingof the carrier may be less than 50%, such as less than 25%, for instanceless than 10%, for example less than about 1%. The carrier may have thesubstantially the same or higher flexibility as a glass, quartz orsilicon wafer.

In an embodiment, the at least one layer of conducting and/orsemiconducting material may be selected from the group comprising:conducting polymers, conducting paste, metals, Fe, Cu, Au, Ag, Pt, Si,SiC, Sn, Pd, Pt, Co, Ti, Ni, Cr, Al, Indium-Tin-Oxide (ITO), SiGe, GaAs,InP, Ru, Ir, Re, Hf, Os, Rh, alloys, phosphorous-alloys, SnAg, PbAg,SnAgCu, NiP, AuCu, silicides, stainless steel, brass, solder materialsand combinations thereof. The at least one layer of conducting materialmay be a metal selected from the group comprising: Cr, Ti, Au, Pt. Theat least one layer of conducting material may comprise Au or Pt. The atleast one layer of semiconducting material may be Si. The insulatingmaterial may be selected from the group comprising: oxides such as SiO₂,quartz, glass, nitrides such as SiN, polymers, polyimide, polyurethane,epoxy polymers, acrylate polymers, PDMS, (natural) rubber, silicones,lacquers, elastomers, nitrile rubber, EPDM, neoprene, PFTE, parylene andcombinations thereof. The insulating material may be applied with amethod selected from the group comprising: thermo-oxidation,Plasma-Enhanced-Chemical-Vapor Deposition (PECVD), Physical VaporDeposition (PVD), Chemical-Vapor-Deposition (CVD), electricalanodization, Atomic-Layer-Deposition (ALD), spin-coating, spray-coating,roller-coating, powder-coating, adhesive taping, pyrolysis, bonding andcombinations thereof.

In an embodiment, the wet-etching or dry-etching methods may compriseusing an etch-mask, which is applied onto a surface, which is not to beetched. The etch-mask may be patterned with a lithography method.

In an embodiment, a planarization step may be performed on said carrier.The conducting electrode layer may comprise at least one layer ofconducting and/or semiconducting material selected from the groupcomprising: Fe, Cu, Sn, Ag, Au, Pd, Co, Ti, Ta, Ni, Pt, Cr, Al, W, ITO,Si, Ru, Rh, Re, Os, Hf, Ir, Nb, other metals, alloys, phosforous-alloys,SnAg, SnAgCu, CoWP, CoWB, CoWBP, NiP, AuCu, silicides, graphite,stainless steel, conducting polymers, solder materials, conducting orsemiconducting oxides or mixed oxides, such as mixtures of oxides ofabove mentioned metals, such as Ru, Ir, Rh, Ti and/or Ta oxides. Theconducting electrode layer may be applied with methods selected from thegroup comprising: ALD, Metallorganic-Chemical-Vapor-Deposition (MOCVD),PVD, CVD, sputtering, electroless deposition, immersion deposition,electrodeposition, electro-grafting, chemical grafting and combinationsthereof. The conducting electrode layer may be applied by using acombination of PVD/sputtering and electroless/immersion deposition. Theconducting electrode layer may be treated by thermal methods. Thethermal methods may be annealing, such as rapid-thermal-annealing (RTA),furnace heating, hot-plate heating or combinations thereof; wherein saidmethods may be performed in an environment which substantiallycomprises: vacuum, forming gas, hydrogen gas, nitrogen gas, low oxygencontent or combinations thereof.

In an embodiment, the conducting electrode layer may be formed byapplying several layers of at least one material and by treating atleast one layer by said thermal methods before applying a next layer. Anadhesion layer may be applied onto at least some parts of the carrierprior to applying said conducting electrode layer; wherein said adhesionlayer may be comprised of one or several materials that increase theadhesion of the conducting electrode layer to said carrier. Theinsulating pattern layer may be comprised of one or several layers of anelectrically insulating material, which is pattered by being providedwith several recesses. The insulating pattern layer may have a lowsurface roughness and high thickness uniformity.

In an embodiment, the at least one electrically insulating layer of saidinsulating pattern layer may be is applied using a method selected fromthe group comprising: thermal oxidation, thermal nitridation, PECVD,PVD, CVD, MOCVD, electrochemical anodization, ALD, spin-coating,spray-coating, dip-coating, curtain-coating, roller-coating,powder-coating, pyrolysis, adhesive taping, bonding and combinationsthereof. An adhesion layer may be arranged onto at least some parts ofsaid carrier prior to arranging said insulating pattern layer; whereinsaid adhesion layer may comprise at least one layer of material thatimproves the adhesion properties between the insulating pattern layerand the carrier. The adhesion layer may be comprised of at least onelayer of a material selected from the group comprising: conductingmaterials such as Pt, Al, Ni, Pd, Cr, Ti, TiW; insulating materials suchas AP-3000, AP-100, AP-200, AP-300, silanes such as HMDS andcombinations thereof. The adhesion layer may be applied using depositionmethods selected from the group comprising: electrodeposition,spin-coating, spray-coating, dip-coating, Molecular-Vapor-Deposition(MVD), ALD, MOCVD, CVD, PVD, sputtering, electroless deposition,immersion deposition, electrografting, chemical grafting andcombinations thereof.

In an embodiment, a planarization step may be performed on the arrangedinsulating pattern layer. The planarization step may be performed by amethod selected from the group comprising: etching and/or polishingmethods such as chemical-mechanical-polishing (CMP), lapping, contactplanarization (CP) and/or dry etching methods such as ion-sputtering,reactive-ion-etching (RIE), plasma-assisted-etching, laser-ablation,ion-milling; and combinations thereof. The electrically insulatingmaterial may be selected from the group comprising: organic compounds,polymers, insulating in-organic compounds, oxides, nitrides, polyimide,siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE),silicones, elastomeric polymers, E-beam resists such as ZEP,photoresists, thinfilm resists, thickfilm resists, polycyclic olefins,polynorborene, polyethene, polycarbonate, PMMA, BARC materials,Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxy polymers,fluoro elastomers, acrylate polymers, (natural) rubber, silicones,lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene,fluoromethylene cyanate ester, inorganic-organic hybrid polymers,fluorinated or hydrogenated amorphous carbon, organic doped siliconglass (OSG), fluorine doped silicon glass (FSG), PFTE/silicon compound,tetraethyl orthosilicate (TEOS), SiN, SiO₂, SiON, SiOC, SiCN:H, SiOCHmaterials, SiCH materials, silicates, silica based materials,silsesquioxane (SSQ) based material, methyl-silsesquioxane (MSQ),hydrogen-silsesquioxane (HSQ), TiO₂, Al₂O₃, TiN and combinationsthereof. The recesses in said insulating pattern layer may be formed byusing lithography, etching methods and/or mechanical abrasive methods.The etching methods may comprise wet-etching and/or dry-etching. Thedry-etching methods may comprise: ion-sputtering, reactive-ion-etching(RIE), plasma-assisted-etching, laser-ablation, ion-milling orcombinations thereof. The etching methods may comprise arranging apatterned etch-mask onto at leas some areas of said insulating patternlayer, said areas being protected from etching. The patterned etch-maskmay be produced by said lithography and/or etching methods. Theetch-mask may be comprised of a polymer resist used in saidlithographical methods such as a thinfilm photoresist, polyimide, BCB, athick film resist and/or other polymers and the like; or a hard-maskcomprising material such as SiN, SiO₂, SiC, Pt, Ti, TiW, TiN, Al, Cr,Au, Cu, Ni, Ag, NiP; or combinations thereof. The hard mask may beapplied with methods selected from the group comprising: PVD, CVD,MOCVD, sputtering, electroless deposition, immersion deposition,electrodeposition, PECVD, ALD and combinations thereof. The etch-maskmay comprise at least one structure layer being formed in said at leastone electrochemical cell formed by a further master electrode.

In an embodiment, the structure layer may be comprised of at least onematerial selected from the group comprising: Cu, Ni, NiFe, NiP Au, Ag,Sn, Pb, SnAg, SnAgCu, SnPb and combinations thereof. An etch-stop layermay be applied prior to applying said insulating pattern layer. Theetch-stop layer may be formed by at least one layer of a materialselected from the group comprising: Ti, Pt, Au, Ag, Cr, TiW, SiN, Ni,Si, SiC, SiO2, Al, InGaP, CoP, CoWP, NiP, NiPCo, AuCo, BLOk™ andcombinations thereof.

In an embodiment, the patterning method for forming said insulatingpattern layer may be modified in order to affect the angle ofinclination for the cavity sidewalls in the insulating pattern layer.The cavity sidewalls of said insulating pattern layer may be close tovertical, whereby the sidewalls have an angle to the normal of the saidconducting electrode surface of less than about 45°, such as less thanabout 20°, such as less than about 5°, such as less than about 2°, suchas less than about 1°, such as less than about 0.1°. The angleinclination may be optimized by varying parameters in aphotolithographic patterning method, such as using wave-length filters,using anti-reflective coatings, modifying the exposure dose, modifyingthe development time, using thermal treatment and/or combinationsthereof. A specific angle of inclination may be obtained by optimizingthe gas composition, platen power (RF power) and/or plasma power (alsocalled coil power) for dry-etching methods such Reactive-Ion-Etching(RIE).

In an embodiment, a damascene process may be used to create the cavitiesof said insulating pattern layer; said damascene process may involveapplying a sacrificial pattern layer, having recesses, onto the carrier;applying an insulating material so that it cover said sacrificialpattern layer as well as fills up the recesses of the sacrificialpattern; planarizing said insulating material until the sacrificialpattern layer is uncovered; and removing said sacrificial pattern layerwhereby an insulating pattern layer is formed. The sacrificial patternmay be arranged by applying a material, which is patterned bylithography, plating and/or etching methods. The sacrificial patternlayer may comprise at least one structure layer being formed in anelectrochemical cell with a further master electrode.

In an embodiment, the method may further comprise a coating of a releaselayer onto at least some parts of the insulating pattern layer; whereinsaid release layer lowers the mechanical and chemical bond between theinsulating pattern layer and other materials being put in contact withsaid layer. The release layer may be applied using spin-coating,spray-coating, CVD, MOCVD, MVD, PVD and/or by combinations thereof; andformed of materials selected from the group comprising: silanes such asmethoxy-silanes, chloro-silanes, fluoro-silanes, siloxanes such aspoly-di-methyl-siloxane, poly-ethylane-glycol-siloxanes,dimethyl-siloxane oligomer (DMS) and/or other polymers such as amorphousfluoro-polymers, fluoro-carbons poly-tetra-fluoro-ethylen (PTFE),Cyto-fluoro-polymers and combinations thereof. The surfaces forming saidat least one electrochemical cell may have surface properties that havegood wetting ability of the electrolyte used in said electrochemicalcell. The surfaces forming said at least one electrochemical cell may behydrophilic, having a low contact angle with aqueous solutions. At leastsome surfaces of said insulating pattern layer may have been treatedwith methods that lower the surface energy, creating hydrophilicsurfaces. At least some surfaces of said insulating pattern layer mayhave been treated with thermal treatment, oxygen/nitrogen/argon plasmatreatment, surface conversion for anti-sticking (SURCAS), strongoxidizing agents such as peroxides, persulfates, concentratedacids/bases or combinations thereof. At least some parts of theinsulating pattern layer may have high surface energy or is treated withmethods, such as hydrogen plasma, in order to increase the surfaceenergy, making the surface hydrophobic. The insulating pattern layer maycomprise one or several layers of at least one material havingproperties such that the side-walls of the cavities of the insulatingpattern layer are hydrophilic and the top of the insulating patternlayer are hydrophobic. The hydrophilic material may be selected from thegroup comprising: SiN, SiO₂, polymers (such as photoresists and/orelastomers) that have been treated with oxygen plasma and/or othermaterials with polar functional molecule groups at the surface andcombinations thereof; and said hydrophobic materials are selected fromthe group comprising: materials with non-polar functional moleculegroups such as hydrogen terminated polymers, Teflon, fluoro- andchloro-silanes, siloxanes, fluoro-elastomers and combinations thereof.

In an embodiment, the insulating pattern layer may comprise one orseveral layers of at least one material, which improves the mechanicalcontact between the top of the insulating pattern layer surface and anintended substrate when the master electrode is pressed against saidsubstrate. The insulating pattern layer may be comprised of at least onelayer a flexible material such an elastomer; or at least one layer ofrigid material and at least one layer of a flexible material. The atleast one layer of flexible materials may be arranged on top of said atleast one layer of rigid material. The flexible material may be anelastomer; said elastomer having properties selected from the groupcomprising: having high compressibility; elastic properties;electrically insulating; low dielectric properties; good chemicalresistance; strong adhesion to underlying layers such as metals,silicon, glass, oxides, nitrides and/or polymers; have high resistanceagainst shrinking or swelling over time and/or; be non-bleeding, meaningnot releasing contaminating organic compounds; sensitive to UW-light;being patterned with lithography methods; being transparent; beingpatterned by using etching methods, such as by dry-etching methods; andcombinations thereof. The elastomer is a material selected from thegroup comprising: Poly-Di-Methyl-Siloxane (PDMS), silicones,epoxy-silicones, fluoro-silicones, fluoro-elastomers, (natural) rubber,neoprene, EPDM, nitrile, acrylate elastomers, polyurethane andcombinations thereof. The elastomer may have a tensile elastic modulus(Young's modulus) less than 0.1 GPa, such as less than 1 MPa, forexample less than about 0.05 MPa; or said elastomer layer have ahardness of less than 90 Shore-A, such as less than 30 Shore-A, forexample less than about 5 Shore-A.

In an embodiment, the carrier or disc may have a circular shape. Thecarrier or disc may alternatively have a rectangular shape. The carrieror disc may be provided with recesses in the same region as the recessesof the insulating pattern layer; said recesses of the carrier may beprovided with a conducting electrode layer. The insulating pattern layermay be provided by bonding and patterning a bond-layer of an insulatingmaterial onto said carrier. The bond-layer may be provided with abond-carrier, which can be removed after the bonding. The bond-layer maybe SiO₂, glass, quartz or a polymer film. The bond-layer may be providedwith an adhesive bond-layer. The bond-carrier may be removed afterbonding using mechanical methods, such as grinding or polishing, oretching methods, such as wet- or dry-etching.

In an embodiment, the master electrode may have a front-side area, whichis substantially the same as the front side area of said substrate. Themaster may be provided with connection sites being recesses or holesthat allow for an external electrical connection to a substrate. Thecarrier or disc may be provided with at least one recess in theperimeter. The carrier or disc may be provided with connection holes inthe perimeter of close to the perimeter.

In an embodiment, the connection sites may be located so as to give auniform current density distribution when forming an electrochemicalcell with the substrate. The master electrode may be provided with anelectrical seed layer connection of a conducting, electrode formingmaterial and being arranged in at least some parts between the recesseson top of said insulating pattern layer. The electrical seed layerconnection may be electrically isolated by an insulating material fromthe conducting or semiconducting materials of the carrier, disc,conducting electrode layer or connection layer. The electrical seedlayer connection may be provided as a layer around the edge of thecarrier or disc. The electrical seed layer connection may be arrangedover a large surface of the insulating pattern layer and substantiallyover the entire surface, except adjacent the edges to the cavities ofthe pattern layer. The different portions of said electrical seed layerconnection may be provided with connection areas at the backside of thecarrier and through the carrier.

In an embodiment, the master electrode further comprises means forreducing an edge bead, which is formed when applying, said insulatingpattern layer with methods such as spin-coating or spray-coating. Thecarrier or disc may be provided with a recess in the perimeter. Aspin-carrier may be used when applying the insulating pattern layer andthe spin-carrier may be provided with a recess in which the carrier isembedded. The edge-bead may be removed by using methods such asdissolving in organic solvents, mechanical removing and/or by removinginsulating pattern layer edge-bead area by lithographical and/or etchingmethods.

In an embodiment, the master electrode may further comprise alignmentmarks, for aligning said master electrode to a substrate; said alignmentmarks comprising structures or cavities in a layer on the front-sideand/or backside of the master electrode. The alignment marks may beprovided in said carrier, conducting electrode layer and/or in saidinsulating pattern layer.

In an embodiment, the carrier may be transparent in the light used foralignment, such as ultra-violet light, infra-red light or X-rays, andwhere the insulating pattern layer is provided with the alignment marks.The conducting electrode layer may be of a non-transparent material andmay be provided with openings in regions where the alignment marks inthe insulating pattern layer are located. The conducting material may betransparent in the light used for alignment. The insulating patternlayer may be of a non-transparent material and may be provided withopenings in regions where alignment marks are arranged in the carrier orconducting electrode layer. The alignment marks may comprise a material,which is non-transparent and is located onto a portion of otherwisetransparent materials, such as metal onto quartz. The alignment marksmay be provided on the backside; and wherein the pattern of theinsulating patter layer is aligned relative to the alignment marks whenarranged on the front-side; or where the alignment marks are aligned tothe pattern of the insulating pattern layer when arranged on thebackside. The alignment marks may be arranged on the front-side, for theuse of a face-to-face alignment method. The alignment marks may bearranged in the insulating pattern layer or conducting electrode layeron the front-side; and the carrier is provided with through-holes in theareas where the alignment marks are located making the alignment markson the front-side visible from the back-side. A transparent material maybe arranged in said through-holes.

In an embodiment, the substrate may comprise topography in at least someparts and the insulating patter layer and may be arranged with a patternthat compensates for or is adapted to said topography. The insulatingpattern layer may be provided with at least one cavity in regionscorresponding to an area with topography on said substrate when themaster electrode and substrate are put into close contact for forming atleast one electrochemical cell. The at least one cavity corresponding toan area with topography may be less deep than the other recesses of theinsulating pattern layer and said at least one cavity corresponding toan area with topography lacks a conducting electrode layer. Theinsulating pattern layer may be provided with cavities of differentheights, by patterning the insulating pattern layer more than once. Theinsulating pattern layer may be formed using said lithographical and/oretching methods, creating cavities reaching down to the carrier orconducting electrode and the insulating pattern layer may be patternedonce more in at least some areas, creating cavities that compensate fortopography on the substrate but do not reach the carrier or conductingelectrode layer. The insulating pattern layer may be patterned usingsaid lithographical and/or etching methods creating cavities thatcompensate for topography on the substrate but do not reach the carrieror conducting electrode layer below and the insulating pattern layer ispatterned once more to create the cavities that reach the carrier orconducting electrode layer below. The insulating pattern layer maycomprise at least two layers of an insulating material and at least oneetch-stop layer; and further performing a patterning sequence at leastonce, wherein said sequence comprise: etching down cavities in a topinsulating pattern layer down to the etch-stop layer; removing portionsof the etch-stop layer using said lithographical and etching methods;and etching another layer of cavities in underlying insulating patternlayer using said patterned etch-stop layer as an etch-mask down to anunderlying etch-stop layer, carrier or conducting electrode layer. Thecavities of the insulating pattern layer may be created as an imprint ofa substrate template having the same or substantially the sametopography as the substrate surface and said insulating pattern layer ispatterned, creating cavities down to the underlying carrier orconducting electrode layer. The insulating pattern layer may be arrangedby at least once performing a sequence comprising: applying a layer ofnegative photoresist and/or a UV-curing polymer; exposing said layer toUV-light through a photomask; applying a further layer of photoresistand/or a UV-curing polymer; exposing said second layer to UV-lightthrough a further photomask; and if necessary, performing anpost-exposure-bake (PEB) step prior to developing both layerssimultaneously. The sequence may comprise using direct write methodssuch as laser-beam or E-beam exposure instead of exposing said layerswith UV-light through a photomask. The insulating pattern layer may bepatterned by repeating said lithography and/or etching steps and therebycreating multiple levels of cavities so as to compensate for multiplelevels of topography of different heights and shapes on a substrate. Theat least one cavity, which is adapted to said topography, may besufficiently large for enclosing the topography inside said cavity withsome margin. The carrier of the master electrode may be provided withrecess in at least one cavity of an insulating pattern layer; saidrecess being coated on the walls with a conducting electrode layer; anda predeposited anode material is arranged onto said conducting electrodelayer. The carrier and the conducting electrode layer may exert aprotruding structure in at least one cavity of an insulating patternlayer; and a predeposited anode material is arranged onto saidconducting electrode layer.

BRIEF DESCRIPTION OF DRAWINGS

Further objects, features and advantages of the invention will appearfrom the following detailed description of several embodiments withreference to the drawings, in which:

FIGS. 1( a) to 1(d) are schematic cross-sectional views of severalmethod steps in forming a master electrode from a conducting orsemiconducting carrier.

FIGS. 2( a) to 2(d) are schematic cross-sectional views of severalmethod steps in forming a master electrode from a non-conductingcarrier.

FIGS. 3( a) to 3(e) are schematic cross-sectional views of severalmethod steps in forming a master electrode from a conducting carrierwith added conducting layer in a pattern.

FIGS. 4( a) to 4(e) are schematic cross-sectional views of severalmethod steps in forming a master electrode with pattern arranged in thecarrier.

FIG. 5 is a schematic cross-sectional view of a master electrode inwhich cells of the pattern are deep.

FIGS. 6( a) to 6(c) are schematic cross-sectional views of severalmethod steps in forming a master electrode with an adhesion layer bondedinsulating pattern layer.

FIG. 7( a) is a schematic cross-sectional view and FIG. 7( b) is a topview of a master electrode applied on a large substrate.

FIG. 7( c) is a schematic cross-sectional view and FIGS. 7( d) to 7(e)are top views of a master electrode provided with one or severalrecesses.

FIGS. 7( f) to 7(i) are schematic cross-sectional views of a masterelectrode provided with contact areas to a substrate.

FIGS. 8( a) to 8(h) are schematic cross-sectional views of a carrierhaving different types of edge recesses.

FIGS. 9( a) to 9(b) are schematic cross-sectional views in which edgebeads are included and mitigated, respectively.

FIGS. 10( a) to 10(c) are schematic cross-sectional views and show amethod for forming a master electrode without edge beads.

FIGS. 11( a) to 11(b) are schematic cross-sectional views and shows amethod for forming a master electrode without edge beads.

FIG. 12( a) is an enlarged cross-sectional view of conductive paths inseveral electrochemical cells.

FIGS. 12( b) to 12(d) are cross-sectional views of master electrodeswith different radial height distribution of plated structures.

FIGS. 13( a) and 13(b) are cross-sectional views similar to FIGS. 12( c)and 12(d) in which the substrate is concave from the start.

FIGS. 14( a) and 14(b) are cross-sectional views similar to FIGS. 13( a)and 13(b) in which the substrate is convex from the start.

FIGS. 15( a) to 15(e) are schematic cross-sectional views of anembodiment of a master electrode provided with three-dimensionalcavities in a pattern layer.

FIGS. 16( a) to 16(c) are schematic cross-sectional views of anotherembodiment of a master electrode provided with three-dimensionalcavities in a pattern layer.

FIGS. 17( a) to 17(e) are schematic cross-sectional views of a furtherembodiment of a master electrode provided with three-dimensionalcavities in a pattern layer.

FIGS. 18( a) to 18(c) are schematic cross-sectional views of a stillfurther embodiment of a master electrode provided with three-dimensionalcavities in a pattern layer.

FIGS. 19( a) to 19(b) are schematic cross-sectional views showing theuse of the embodiment of the master electrode of FIGS. 18( a) to 18(c).

FIG. 20( a) is a schematic cross-sectional view of a yet furtherembodiment of a master electrode provided with three-dimensionalcavities in a pattern layer.

FIGS. 20( b) to 20(d) are schematic cross-sectional views showing theuse of the embodiment of the master electrode of FIG. 20( a).

FIGS. 21( a to 21(b) are schematic cross-sectional views showing anembodiment of the master electrode having cavities of different depthswith an uneven distribution of predeposited material.

FIGS. 22( a to 22(b) are schematic cross-sectional views showing anotherembodiment of the master electrode having cavities with an unevendistribution of predeposited material.

FIG. 23( a) is a schematic cross-sectional view showing how a conductingelectrode layer of an electrode is dissolved in an electrochemical celland are undercutting the insulating pattern layer of said electrode.

FIG. 23( b) is a schematic cross-sectional view showing how an anodematerial, being predeposited onto a conducting electrode layer of anelectrode, is dissolved in electrochemical cells and said conductingelectrode layer being intact.

DETAILED DESCRIPTION OF EMBODIMENTS

Below, several embodiments of the invention will be described withreferences to the drawings. These embodiments are described inillustrating purpose in order to enable a skilled person to carry outthe invention and to disclose the best mode. However, such embodimentsdo not limit the invention, but other combinations of the differentfeatures are possible within the scope of the invention.

Some general remarks are given below with regard to the master electrodeand methods of forming the master electrode. Several methods aredescribed for forming a master electrode that can be used for producingone or multiple layers of structures of one or multiple materialsincluding using an electrochemical pattern replication (ECPR) technologydescribed below. The methods generally include: forming a masterelectrode that comprises a carrier which is conducting/semiconducting inat least some parts; forming a conducting electrode layer whichfunctions as anode in ECPR plating and cathode in ECPR etching; andforming an insulating pattern layer that defines the cavities in whichECPR etching or plating can occur in the ECPR process; in a way thatmakes possible electrical contact from an external power supply to theconducing parts of the carrier and/or to the conducting electrode layer.

The master electrode is to be used for producing one or multiple layersof structures using the electrochemical pattern replication (ECPR)technology including the following three steps, namely:

a) putting a master electrode in contact with the substrate, such as aseed layer, to form multiple electrolytic cells;

b) forming structures in said seed layer by etching or formingstructures on said seed layer by plating; and

c) separating said master electrode from said substrate.

In a first step (a) a master electrode comprising an electricallyconducting electrode layer, of at least one an inert material, such asplatinum, and an insulating pattern layer, is put in close physicalcontact with the conducting top layer or seed layer, on the substrate inthe presence of an electrolyte, forming electrochemical cells, filledwith electrolyte, defined by the cavities of the insulating structureson the master.

Said seed layer can comprise one or several layers of metals such as Ru,Os, Hf, Re, Rh, Cr, Au, Ag, Cu, Pd, Pt, Sn, Ta, Ti, Ni, Al, alloys ofthese materials, Si, other materials such as W, TiN, TiW, NiB, NiP, NiCoNiBW, NiM-P, W, TaN, Wo, Co, CoReP, CoP, CoWP, CoWB, CoWBP, conductingpolymers such as polyaniline, solder materials such as SnPb, SnAg,SnAgCu, SnCu alloys such as monel, permalloy and/or combinationsthereof. The seed layer of the substrate can be cleaned and activatedbefore usage in the ECPR process. The cleaning method can include theuse of organic solvents e.g. acetone or alcohols; and/or inorganicsolvents e.g. nitric acid, sulfuric acid, phosphoric acid, hydrochloricacid, acetic acid, hydrofluoric acid, strong oxidizing agents, e.g.peroxides, persulfates, ferric-chloride, and/or de-ionized water.Cleaning can also be performed by applying oxygen plasma, argon plasmaand/or hydrogen plasma or by mechanically removing impurities.Activation of the seed layer surface can be performed with solutionsremoving oxides, e.g. sulfuric acid, nitric acid, hydrochloric acid,hydrofluoric acid, phosphoric acid and etchants, e.g. sodium-persulfate,ammonium-persulfate, hydrogen-peroxide, ferric-chloride and/or othersolutions comprising oxidizing agents.

Putting the master electrode in close contact with the top layer on thesubstrate includes aligning the master electrode insulating pattern tothe patterned layer on the substrate. This step can include the use ofalignment marks on the front side or backside of the master electrodethat can be aligned to the corresponding alignment marks on thesubstrate. The alignment procedure can be performed before or afterapplying the electrolyte. Predeposited anode material may previously bearranged onto said conducting electrode layer in the cavities of theinsulating pattern layer prior to putting the master in contact with asubstrate. Predeposited anode material in the master electrode cavitiescan be cleaned and activated in advance, in the same manner as describedfor the substrate seed layer, before putting the master into contactwith the substrate.

Said electrolyte comprises a solution of cations and anions appropriatefor electrochemical etching and/or plating, such as conventionalelectroplating baths. For instance, when the ECPR etched or platedstructures are copper, a copper sulphate bath can be used, such as anacidic copper sulphate bath. Acidic may include a pH<4, such as betweenpH=2 and pH=4. In some embodiments, additives can be used, such assuppressors, levellers and/or accelerators, for instance PEG(poly-ethylene glycol) and chloride ions and/or SPS (bis(3-sulfopropyl)disulfide). In another example, when the ECPR etched or platedstructures are Ni, a Watt's bath can be used. Appropriate electrolytesystems for different materials of ECPR etched or plated structures aredescribed in: Lawrence J. Durney, et. al., Electroplating EngineeringHandbook, 4th ed., (1984).

In a second step (b) structures of conducting material are formed usingECPR etching or plating by applying a voltage, using an external powersource, to the master electrode and to the seed layer on the substratefor creating an electrochemical process simultaneously inside each ofthe electrochemical cells defined by the cavities of the masterelectrode and the top layer on the substrate. When the voltage isapplied in such a manner that the seed layer on the substrate is anodeand the conducting electrode layer in the master electrode is cathode,the seed layer material is dissolved and at the same time material isdeposited inside the cavities of the master electrode. The groovescreated by dissolving the seed layer separate the remaining structuresof the seed layer. The structures formed from the remaining seed layeris a negative image of the cavities of the insulating pattern layer ofthe master electrode; and these structures are referred to as “ECPRetched structures” below in this specification. When the voltage isapplied in such a manner that the conducting electrode layer in themaster electrode is anode and the seed layer of the substrate iscathode, the predeposited anode material inside the cavities of themaster electrode is dissolved and at the same time material is depositedon the conducting layer on the substrate in the cavities that are filledwith electrolyte. The deposited material on the conducting layer on thesubstrate forms structures that are a positive image of the cavities ofthe insulating pattern layer of the master electrode; and thesestructures are referred to as “ECPR plated structures” below in thisdescription.

Said ECPR etched or ECPR plated structures can be comprised ofconducting materials, such as metals or alloys, for instance Au, Ag, Ni,Cu, Sn, Pb and/or SnAg, SnAgCu, AgCu and/or combinations thereof, forexample Cu.

In one embodiment, said anode material is predeposited in the cavitiesof the master electrode by using ECPR etching of a material, which isanode, and depositing said material onto the conducting electrode, whichis cathode, in the cavities of the insulating pattern layer of themaster electrode. In other embodiments, said anode material ispredeposited by regular electroplating, electroless plating, immersionplating, CVD, MOCVD, (charged) powder-coating, chemical graftning and/orelectrografting said material selectively onto the conducting electrodelayer in the cavities of the insulating pattern layer of the masterelectrode.

The voltage can be applied in a manner that improves the uniformityand/or properties of the etched and/or plated structures. The appliedvoltage can be a DC voltage, a pulsed voltage, a square pulsed voltage,a pulse reverse voltage and/or a combination thereof.

The uniformity of the etched and/or plated structures can be increasedby choosing an optimized combination of applied voltage waveform,amplitude and frequency. The etch depth or plating height can becontrolled by monitoring the time and the current passing through themaster electrode. If the total electrode area is known, the currentdensity can be predicted from the current passing through the electrodearea. The current density corresponds to an etching or plating rate andhence the etching depth or plating height can be predicted from theetching or plating rate and time.

In some embodiments, the etching or plating process is stopped bydisconnecting the applied voltage before reaching the underlying surfaceof the dissolving anode material. For the etching process, this meansthat the process is stopped when a layer is still remaining in thebottom of the etched grooves in the seed layer, covering the underlyingsubstrate layer. Otherwise, there is a risk that the electric connectionto certain portions of the seed layer may be broken. For the platingprocess, this means that the process is stopped when a layer ofpredeposited anode material still remains, such as 5% to 50%, coveringthe conducting electrode layer. Otherwise, uneven current distributionmay occur in the respective electrochemical cells.

In some embodiments, the desired height of the plated structures aresignificantly less than the thickness of the predeposited anodematerial. This implies that several layers of structures can be platedonto one or several substrates before having to predeposit new anodematerial. In some examples the height of the predeposited material canbe at least twice as thick as the height of the plated structures.

In some embodiments, multiple layers of ECPR plated structures areapplied directly onto each other.

In a third step (c) after the ECPR etched or plated structures areformed, the master is separated from the substrate in a manner thatminimizes damages on the master or on the ECPR etched or platedstructures on the substrate. The method can be performed by holding thesubstrate in a fixed position and moving the master electrode in adirection perpendicular to the substrate surface or by holding themaster electrode in a fixed position and moving the substrate in adirection perpendicular to the master electrode surface. In otherembodiments, the separation can be performed in a less parallel mannerin order to ease the separation. After the ECPR etching or plating step,remaining material deposited inside the cavities of the master electrodecan be removed using removal methods that include applying wet etchingchemicals suitable for dissolving the remaining materials. Ananisotropic etching method can also be used for instance withdry-etching methods such as ion-sputtering, reactive-ion-etching (RIE),plasma-assisted-etching, laser-ablation, ion-milling. In someembodiments, said removal methods include a combination of dry-etchingand wet-etching methods. The remaining material can in some embodimentsalso be removed by regular plating and/or ECPR plating onto any cathodeand/or dummy substrate respectively. In some embodiments this is doneprior to using the master electrode in another ECPR etching step orprior to predepositing new material inside the cavities of the masterused for the ECPR plating step. Alternatively, during plating, only aportion of the predeposited material may be used in a single procedureand another portion of the predeposited material may be used in the nextprocedure, for a number of procedures. Alternatively, during etching,the material deposited on the cathode, i.e. the master electrode, maynot need to be removed between each procedure, but may be removedbetween each second, third etc procedure.

Three embodiments of methods for forming a master electrode generallycomprises the following steps:

1. supplying an insulating or conducting/semiconducting carrier

2. applying a conducting electrode layer onto at least some parts ofsaid carrier

3. applying an insulating pattern layer onto at least some parts of saidconducting electrode layer

or

1. supplying an insulating or conducting/semiconducting carrier

2. applying an insulating pattern layer onto at least some parts of saidcarrier

3. applying a conducting electrode layer onto selected parts of saidcarrier which are not covered by said insulating pattern layer

or

1. supplying and patterning a conducting/semiconducting carrier

2. applying an insulating pattern layer onto at least some parts of saidpatterned carrier

3. applying a conducting electrode layer into selected parts of saidpatterned carrier that is not covered by said insulating pattern layer.

The materials used for the portions of the master electrode that areexposed to the chemical and/or electrochemical environment during ECPRetching, ECPR plating, predeposition, cleaning and/or removal methods,are generally resistant to dissolution and oxidation in said chemicaland/or electrochemical environment.

In one embodiment, said conducting electrode layer is applied onto saidcarrier and said insulating pattern layer is applied onto the conductingelectrode layer.

In another embodiment, said insulating pattern layer is applied ontosaid carrier and said conducting electrode layer is applied onto atleast some parts of the carrier inside the cavities of the insulatingpattern layer.

In still another embodiment, recesses are created in said carrier andsaid insulating pattern layer is applied in areas of the carrier, whichare not provided with the recesses, while said conducing electrode layeris applied onto the carrier in the bottom of and onto the walls of therecesses that are not covered by the insulating pattern layer.

Said carrier may comprise one or several layers of:

at least one conducting/semiconducting material; or

at least one conducting/semiconducting material and at least one layerof insulating material.

Said layers of said carrier can be flexible and/or rigid and/or acombination of flexible and rigid layers. In some embodiments, saidcarrier is rigid enough to avoid bending down significantly into thecavities of said insulating pattern when applying the force needed toput the master electrode in contact with a substrate, thereby avoiding ashort circuit contact between the carrier and the substrate during ECPRetching and/or ECPR plating. For instance, the distance that the carrierbends down when applying required pressure should be less than 50% ofthe height of the cavities, such as less than 25%, for example less than10%, for instance less than about 1%. In one embodiment, said carrier isflexible enough to compensate for waviness and/or unevenness of thesubstrate when a distributed force is applied to put the master intocontact with the substrate during ECPR etching and/or ECPR plating. Insome cases, the carrier is at least as flexible as the substrate. Forinstance, the substrate can be a glass, quartz or silicon wafer. In thisexample, the master electrode carrier can have the same or higherflexibility as a glass, quartz or silicon wafer, respectively.

The conducing/semiconducting material can be of materials such asconducting polymers, conducting paste, metals, Fe, Cu, Au, Ag, Pt, Si,SiC, Sn, Pd, Pt, Co, Ti, Ni, Cr, Al, Indium-Tin-Oxide (ITO), SiGe, GaAs,InP, Ru, Ir, Re, Hf, Os, Rh, alloys, phosphorous-alloys, SnAg, PbAg,SnAgCu, NiP, AuCu, silicides, stainless steel, brass, conductingpolymers, solder materials and/or combinations thereof. The insulatinglayer can be comprised of oxides such as SiO₂, Al2O3, TiO2, quartz,glass, nitrides such as SiN, polymers, polyimide, polyurethane, epoxypolymers, acrylate polymers, PDMS, (natural) rubber, silicones,lacquers, elastomers, nitrile rubber, EPDM, neoprene, PFTE, paryleneand/or other materials used for said insulating pattern layer mentionedbelow.

In one embodiment, the carrier comprises a conducing/semiconducting discthat is covered by an insulating material coating over at least someparts. The insulating material coating may be applied so that it coversall parts of said conducting/semiconducting disc except for the centerparts on the front- and back-side. The insulating material coating canbe applied by methods such as thermo-oxidation,Plasma-Enhanced-Chemical-Vapor Deposition (PECVD), Physical VaporDeposition (PVD), Chemical-Vapor-Deposition (CVD), Flame HydrolysisDeposition (FHD), electrical anodization, Atomic-Layer-Deposition (ALD),spin-coating, spray-coating, roller-coating, powder-coating, adhesivetaping, pyrolysis, bonding by other suitable coating techniques and/orcombinations thereof. The insulating material coating can be appliedselectively to the intended parts of said conducting/semiconducting discor by applying it to the entire conducting/semiconducting disc followedby removing parts of the insulating material coating in selected areas.For instance, the insulating material coating can be removed by etchingmethods, such as by using an etch-mask to protect the areas where theinsulating material coating should be intact and/or by using mechanicalremoving methods.

Said etching methods can be wet-etching and/or dry-etching methods.Wet-etching is performed by applying liquid chemicals that dissolve thematerial intended to be etched, said chemicals often including strongoxidizing chemicals such as strong acids and the like. For instance,buffered, diluted or concentrated hydrofluoric acid can be used to etchSiO₂ and other oxides. Said dry-etching methods can include methods suchas ion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching,laser-ablation, ion-milling. The pattern of the etch-mask can beproduced with lithographical methods such as photolithography, laserlithography, E-beam lithography, nanoimprinting and/or otherlithographic processes suitable for patterning the etch-mask. Saidetch-mask can be a polymer material, for instance a resist used in saidlithographical methods such as a thinfilm photoresist, polyimide, BCBand/or a thick film resist. The etch-mask can also be a hard-maskcomprising material such as SiN, SiC, SiO₂, Pt, Ti, TiW, TiN, Al, Cr,Au, Ni, other hard materials and/or by combinations thereof. Thehard-mask is patterned by said lithographical methods followed byetching the hard-mask selectively in the areas not covered by thepatterned lithography mask. Said mechanical removing methods can includepolishing, grinding, drilling, ablation, (sand or fluid) blasting and/orcombinations thereof.

In another embodiment, the carrier comprises an insulating disc with atleast some parts being of conducting/semiconducting material. In thiscase, the conducting/semiconducting part may be applied in the center ofthe insulating disc. In one embodiment, the carrier is formed bycreating cavities in the insulating material disc in selected area andapplying conducing/semiconducting material in the cavities. The cavitiesin the insulating disc can be formed by said wet-etching methods, saiddry-etching methods and/or by said mechanical removing methods. Saidetch-mask can be used in the method for creating the cavities and theetch-mask can be patterned with said lithographic methods. Methods forapplying said conducting/semiconducting material in the cavities can bePVD, CVD, sputtering, electroless deposition, immersion deposition,electrodeposition, chemical grafting, electro-grafting, mechanicalplacement, soldering, gluing, by other suitable deposition methodsand/or by combinations thereof. In some embodiments, a planarizationstep can be performed on the carrier in order to increase the planarityand to reduce surface roughness.

Said conducting electrode layer can be comprised of one or severallayers of a conducting/semiconducting material. For instance, theconducting electrode layer can be comprised of Fe, Cu, Sn, Ag, Au, Pd,Co, Ti, Ta, Ni, Pt, Cr, Al, W, ITO, Si, Ru, Rh, Re, Os, Hf, Ir, Nb,other metals, alloys, phosforous-alloys, SnAg, SnAgCu, CoWP, CoWB,CoWBP, NiP, AuCu, silicides, graphite, diamond, stainless steel,conducting polymers, solder materials, conducting or semiconductingoxides or mixed oxides (for instance mixtures of oxides of abovementioned metals, such as ruthenium, iridium, rhodium, titanium and/ortantalum oxides) and/or combinations thereof. The conducting electrodelayer can be applied to the carrier by methods such as ALD,Metallorganic-Chemical-Vapor-Deposition (MOCVD), PVD, CVD, sputtering,electroless deposition, immersion deposition, electrodeposition,electro-grafting, other suitable deposition methods and/or combinationsthereof. In some embodiments, said conducting electrode layer can bedeposited selectively onto conducting/semiconducting surfaces usingmethods such as electroless deposition, electrodeposition, immersiondeposition, electrografting, chemical grafting, selective CVD and/orselective MOCVD.

In some embodiments, the conducting electrode layer is treated bythermal methods. Said thermal methods may be performed in high vacuum,forming gas, hydrogen gas, nitrogen gas, gas environments with lowoxygen content and/or by combinations thereof. Said thermal methods canbe annealing (e.g. rapid-thermo-annealing (RTA)), furnace treatment,flame anneal, hot-plate treatment and/or combinations thereof. Saidthermal methods can in some embodiments improve the adhesion between theconducting electrode layer and the carrier and/or improve the electricaland/or mechanical properties of the master electrode (such as hardnessand/or wear resistance), by reducing internal stress and/or contactresistance to said carrier. In some embodiments, the conductingelectrode layer is formed by applying several layers of at least onematerial and by treating at least one layer by said thermal methodsbefore applying a next layer.

In one embodiment, an adhesion layer is applied onto at least some partsof the carrier prior to applying said conducting electrode layer. Saidadhesion layer can be comprised of a material or several materials thatincrease the adhesion of the conducting electrode layer to the carrier.The adhesion layer may be comprised of a conducting material such as Pt,Al, Ni, Pd, Cr, Ti, TiW or an insulating material such as AP-3000 (DowChemicals), AP-100 (Silicon Resources), AP-200 (Silicon Resources),AP-300 (Silicon Resources), silanes such as HMDS and/or combinationsthereof. If necessary, the adhesion layer is not covering all areas ofsaid carrier in order to enable an electrical connection to saidcarrier, such as when the adhesion layer is insulating. Alternativelythe adhesion layer is applied covering the entire carrier and then someparts are removed in areas where electrical connection is requiredbetween the conducting electrode layer and the carrier, for instance inthe center of the front-side. The adhesion layer can in some embodimentsalso function as a catalytic layer facilitating or improving thedeposition of the conducting electrode layer. The adhesion layer can beapplied by using deposition methods such as electrodeposition,spin-coating, spray-coating, dip-coating, Molecular-Vapor-Deposition(MVD), ALD, MOCVD, CVD, PVD, sputtering, electroless deposition,immersion deposition, electrografting, chemical grafting and/or otherdeposition methods suitable for the adhesion material.

Said insulating pattern layer can be comprised of one or several layersof patterned electrically insulating material. The insulating patternlayer may be applied with methods giving low surface roughness and highthickness uniformity of the layer. In some embodiments, the insulatingpattern layer can be applied using methods such as thermal oxidation,thermal nitridation, PECVD, PVD, CVD, Flame Hydrolysis Deposition (FHD),MOCVD, electrochemical anodization, ALD, spin-coating, spray-coating,dip-coating, curtain-coating, roller-coating, powder-coating, pyrolysis,adhesive taping, bonding, by other deposition techniques and/or bycombinations thereof.

In one embodiment, an adhesion layer is applied prior to applying theinsulating pattern layer onto said carrier. Said adhesion layer maycomprise at least one layer of at least one material that improves theadhesion properties between the insulating pattern layer and the surfaceof said carrier. Said adhesion layer may be comprised of an insulatingor conducting material. Said adhesion layer can for instance becomprised of Pt, Ni, Al, Cr, Ti, TiW, AP-3000 (Dow Chemicals), AP-100(Silicon Resources), AP-200 (Silicon Resources), AP-300 (SiliconResources), silanes such as HMDS, Bottom-Anti-Reflective-Coating (BARC)materials and/or combinations thereof. The adhesion layer can be appliedusing methods such as PECVD, PVD, CVD, MOCVD, ALD, spin-coating,spray-coating, roller-coating, powder-coating and/or by combinationsthereof.

In some embodiments, a planarization step can be performed on theapplied insulating pattern layer in order to achieve a more planarsurface. Said planarization step can be done prior to patterning theinsulating pattern layer. Said planarization methods can include etchingand/or polishing methods such as chemical-mechanical-polishing (CMP),lapping, contact planarization (CP) and/or dry etching methods such asion-sputtering, reactive-ion-etching (RIE), plasma-assisted-etching,laser-ablation, ion-milling and/or by other planarization methods and/orby combinations thereof.

The insulating pattern layer can be comprised of organic compounds, suchas polymers, as well as insulating in-organic compounds such as oxidesand/or nitrides. Used polymer materials can for instance be: polyimide,siloxane modified polyimide, BCB, SU-8, polytetrafluoroethylene (PTFE),silicones, elastomeric polymers, E-beam resists (such as ZEP(Sumitomo)), photoresists, thinfilm resists, thickfilm resists,polycyclic olefins, polynorborene, polyethene, polycarbonate, PMMA, BARCmaterials, Lift-Off-Layer (LOL) materials, PDMS, polyurethane, epoxypolymers, fluoro elastomers, acrylate polymers, (natural) rubber,silicones, lacquers, nitrile rubber, EPDM, neoprene, PFTE, parylene,fluoromethylene cyanate ester, inorganic-organic hybrid polymers,(fluorinated and/or hydrogenated) amorphous carbon, by other polymersand/or by combinations thereof. Used in-organic compounds can forinstance be organic doped silicon glass (OSG), fluorine doped siliconglass (FSG), PFTE/silicon compound, tetraethyl orthosilicate (TEOS),SiN, SiO₂, SiON, SiOC, SiCN:H, SiOCH materials, SiCH materials,silicates, silica based materials, silsesquioxane (SSQ) based material,methyl-silsesquioxane (MSQ), hydrogen-silsesquioxane (HSQ), TiO₂, Al₂O₃,TiN and/or combinations thereof. The insulating pattern layer materialsmay have properties that ease the patterning process (lithography and/oretching), have good adherence to the underlying layer, have goodmechanical durability and/or are inert during the ECPR process and/orintermediate cleaning and/or removal steps.

In some embodiments, the pattern (cavities) of the insulating patternlayer is fabricated using methods such as lithography and/or etching.Said lithography methods can include photolithography, UV-lithography,laser-lithography, electron-beam (E-beam) lithography, nanoimprint,other lithographic methods and/or combinations thereof.

Said insulating pattern layer can have different heights depending onthe desired size and height of the ECPR etched or plated structures. Insome embodiments, said insulating pattern layer can have a thickness upto a few hundred microns. In other embodiments, the insulating patternlayer can be thin, such as down to 20 nm. In some embodiments, theheight/width ratio of a cavity (called aspect ratio) is less than 10,such as less than about 5, for instance less than about 2, for exampleless than about 1. In some embodiments, such as for above-ICapplications, the insulating pattern layer is less than about 50 μm, forinstance less than about 15 μm, such as less than about 5 μm, with anaspect ration of less than about 5, for instance less than about 2, suchas less than about 1. In some embodiments, such as for IC interconnectapplications, the insulating pattern layer is less than about 2 μm suchas for IC interconnect global wiring, such as less than 500 nm such asfor IC interconnect intermediate wiring, for example less than 200 nmsuch as for IC interconnect intermediate wiring, such as less than about100 nm such as for IC interconnect “Metal 1” wiring, for instance lessthan about 50 nm such as for IC interconnect “Metal 1” wiring. Sincethere is no forced convection inside said electrochemical cells, thelimiting maximum current and hence the maximum plating/etching rate isdetermined by the properties of the electrolyte and distance between theelectrodes, i.e. the height of the insulating pattern layer. A higherlimiting current is achieved using electrolytes comprising higherconcentration of ions of the material being electrochemically etched ordeposited. Furthermore, less distance between the conducting electrodelayer and the seed layer of the substrate results in higher limitingcurrent. However, short distance, i.e. thin insulating pattern layer,increases the risk of getting short circuits. The thickness of thestructure layer to be formed can be less than about 90% of theinsulating layer thickness, such as less than about 50%, for exampleless than about 10%.

Said etching methods include using an etch-mask to protect the areaswhere the insulating pattern layer should be intact and/or by usingmechanical removing methods. Etching methods can include wet-etchingand/or dry etching methods such as ion-sputtering, reactive-ion-etching(RIE), plasma-assisted-etching, laser-ablation, ion-milling. The patternof the etch-mask can be produced with said lithographical methods. Theetch-mask can be a polymer resist used in said lithographical methodssuch as a thinfilm photoresist, polyimide, BCB, a thick film resistand/or other polymers and the like. The etch-mask can also be ahard-mask comprising material such as SiN, SiO₂, SiC, Pt, Ti, TiW, TiN,Al, Cr, Au, Cu, Ni, Ag, NiP, other hard materials, alloys thereof and/orcombinations thereof. Said hard-mask can be applied with methods such asPVD, CVD, MOCVD, sputtering, electroless deposition, immersiondeposition, electrodeposition, PECVD, ALD, other suitable depositionmethods and/or combinations thereof. The hard-mask is in someembodiments patterned by said lithographical methods followed by etchingthe hard-mask, selectively in the areas not covered by the patternedlithography mask, using wet- and/or dry-etching methods.

In some embodiments, said hard-mask can comprise at least one layer ofECPR etched or plated structures, for instance when the materials usedfor the hard-mask are Cu, Ni, NiFe, NiP Au, Ag, Sn, Pb, SnAg, SnAgCu,SnPb and/or combinations thereof. In this case, the insulating patternlayer of a master electrode can be patterned by using another masterelectrode, in combination with said etching methods, and otherlithographical methods may not be required.

In some embodiments, an etch-stop layer is applied prior to applyingsaid insulating pattern layer. Said etch-stop layer comprises at leastone layer of one or several materials that are less affected by theetching process than the insulating pattern layer, thereby stopping orslowing down the etching process thus protecting the underlying layerwhen the etching has gone through the insulating pattern layer. Saidetch-stop layer can comprise materials such as: Ti, Pt, Au, Ag, Cr, TiW,SiN, Ni, Si, SiC, SiO₂, Al, InGaP, CoP, CoWP, NiP, NiPCo, AuCo, BLOk™(Applied Materials) or other materials less affected by said etchingmethods and/or combinations thereof.

In one embodiment, the said patterning methods can be modified in orderto affect the angle of inclination of the pattern cavity sidewalls inthe insulating pattern layer. The angle of inclination depends on theapplication of the ECPR etched or plated structures. In someembodiments, close to vertical sidewalls (close to 90 degree angle ofinclination between the sidewalls of the insulating pattern layer andthe carrier surface, vertical means in relation to a normal position ofthe structure in which it is horizontal) are used in order to achievecertain electrical properties. This means that the sidewalls have anangle to the normal of the electrode surface (angle of inclination) ofless than about 1°, such as less than about 0.1°. In other embodiments,a larger angle of inclination is used in order to improve the separationmethod of the master electrode from the ECPR plated structures withoutcausing damages either on the insulating pattern layer or on the ECPRplated structures. Such an angle may be up to about 45°, such as up to20°, for example up to about 5°. Said separation method can be improvedby modifying said angle of inclination so that it is more than zerodegrees, which means that the cavities of the insulating pattern layerhave an open area at the top which is larger than at the bottom(generally called “positive angle of inclination”). The angle should notbe substantially negative.

In some embodiments, photoresists used for creating the insulatingpattern layer, by using said lithographic methods may have chemical andphysical properties that give vertical side walls or a positive angle ofinclination. For instance, negative photoresists such as SU-8(Microchem), THB (JSR Micro) or E-beam resists such as ZEP (Sumitomo)can be used in order to achieve an angle of inclination which is closeto zero. Other positive photoresists such as AZ® AX™, AZ® P9200, AZ®P4000 (AZ Electronic Materials), ARF resists (JSR Micro), SPR resists(Rohm & Haas Electronic Materials) and/or other positive photoresistscan be used for creating an insulating pattern layer with a positiveangle of inclination. The angle of inclination can also be adjusted bymodifying parameters of the photolithographic methods. For instance, theangle of inclination of the side walls can be varied by modifying thedepth of focus when exposing the photoresist through a projection lens.Also, the angle of inclination can be optimized by varying parameters ina photolithographic patterning method, for instance: using wave-lengthfilters, using anti-reflective coatings, modifying the exposure dose,modifying the development time, using thermal treatment and/orcombinations thereof.

In another embodiment, said etching methods used for patterning saidinsulating pattern layer can be modified in order to achieve a verticalside wall or positive angle of inclination. For instance, a certainangle of inclination can be obtained by optimizing the gas composition,platen power (RF power) and/or plasma power (also called coil power) fordry-etching methods such Reactive-Ion-Etching (RIE). Said gascomposition can for instance comprise fluorocarbon, oxygen, hydrogen,chlorine and/or argon. The angle of inclination can be controlled bymodifying the level of polymerization of passivating substances on thesidewalls. For instance, by increasing or decreasing the level offluoro-carbon in the gas composition, the level of polymerizationincreases or decreases respectively which in turn results in anincreased (less vertical) or decreased (more vertical) angle ofinclination, respectively. Further, the degree of polymerization can becontrolled by: modifying the oxygen and/or hydrogen content byincreasing the oxygen level which reduces polymerization and give asmaller angle of inclination (more vertical) and vice versa; and/or byincreasing the hydrogen level which increases polymerization and give alarger angle of inclination (less vertical) and vice versa. In someembodiments, said angle of inclination is decreased (made more vertical)by decreasing said coil power while holding said platen power constant.This increases the sputtering effect and thereby results in morevertical side walls when etching said insulating pattern layer. Byinstead increasing said coil power the opposite effect can be achievedthereby resulting in a larger angle of inclination (less vertical). Inanother embodiment, said angle of inclination is decreased (morevertical) by increasing said platen power while said coil power is heldconstant. A larger angle of inclination (less vertical) when etchingsaid insulating pattern layer can be achieved by decreasing said platenpower while said coil power is held constant.

In yet another embodiment, a damascene process can be used to the createthe cavities (pattern) of said insulating pattern layer; said damasceneprocess involving firstly applying a sacrificial pattern layer onto acarrier; secondly applying an insulating material so that it cover saidsacrificial pattern layer as well as fills up the cavities of thesacrificial pattern, by using said application methods mentioned abovefor the insulating pattern layer; planarizing said insulating material,using planarization methods mentioned above, until the sacrificialpattern layer is uncovered; and removing said sacrificial pattern layerwhereby an insulating pattern layer is formed. Said sacrificial patternlayer can for instance be formed by ECPR etching or plating a structurelayer or by using known lithographical and/or etching/plating methods.This alternative patterning method can for instance be used forembodiments including an insulating pattern layer material which isdifficult to pattern directly with lithography and/or etching methods.

In an embodiment, said insulating pattern layer surface can be treatedin order to improve better separation from the ECPR plated structures.For instance, the insulating pattern layer surface can be treated withmethods that give an anti-sticking effect between the side-walls of saidcavitites and the side-walls of ECPR plated structures. This can includecoating said insulating pattern layer surface with a release layer thatdecreases the mechanical and chemical bonds to ECPR plated structures.Such a release layer can be applied using spin-coating, spray-coating,CVD, MOCVD, MVD, PVD and/or by combinations thereof. Said release layercan comprise: silanes such as methoxy-silanes, chloro-silanes,fluoro-silanes, siloxanes such as poly-di-methyl-siloxane,poly-ethylane-glycol-siloxanes, dimethyl-siloxane oligomer (DMS) and/orother polymers such as amorphous fluoro-polymers, fluoro-carbonspoly-tetra-fluoro-ethylen (PTFE), Cyto-fluoro-polymers and/orcombinations thereof.

In one embodiment, the materials used for the insulating pattern layerhave properties and/or are treated with methods that improve the abilityof getting said electrolyte to wet and to fill up the cavities of theinsulating pattern. In one embodiment, at least some parts of theinsulating pattern layer materials have low surface energy propertiesand are hydrophilic, i.e. have a low contact angle with aqueoussolutions. Furthermore, some parts of the insulating pattern layermaterial can be treated with methods that lower the surface energy andcreate hydrophilic surfaces. Such surface treatment methods can forinstance be thermal treatment, oxygen/nitrogen/argon plasma treatment,surface conversion for anti-sticking (SURCAS) and/or treating thesurface with strong oxidizing agents such as peroxides, persulfates,concentrated acids/bases and/or combinations thereof. In otherembodiments, at least some parts of the insulating pattern layer havehigh surface energy or can be treated with methods in order to increasethe surface energy making the surface hydrophobic. Such methods caninclude treatment with hydrogen plasma. In an embodiment, the insulatingpattern layer comprises one or several layers of at least one materialhaving properties such that the side-walls of the cavities of theinsulating pattern layer become hydrophilic and the top of theinsulating pattern layer becomes hydrophobic. Said hydrophilic materialcan be for instance be SiN, SiO₂, polymers (such as photoresists and/orelastomers) that have been treated with oxygen plasma and/or othermaterials with polar functional molecule groups at the surface and/orcombinations thereof. Said hydrophobic material can be materials withnon-polar functional molecule groups such as hydrogen terminatedpolymers, Teflon, fluoro- and chloro-silanes, siloxanes,fluoro-elastomers and/or combinations thereof.

In another embodiment, the insulating pattern layer can have one orseveral layers of at least one material which improve the mechanicalcontact between the top of the insulating pattern layer surface and theseed layer surface of the substrate when the master electrode is pressedagainst said seed layer. As mentioned above, the insulating patternlayer can be comprised of at least one layer of flexible materials suchas elastomers. In one embodiment, the insulating pattern layer comprisesat least one layer of rigid material and at least one layer of saidelastomer material. Said layers of elastomer material may be applied ontop of said layers of rigid material. Said elastomer layer can: havehigh compressibility and/or elastic properties; be electricallyinsulating and/or have low dielectric properties; have good chemicalresistance against the environment used in the ECPR process and/orintermediate cleaning and/or removal steps, for instance against saidelectrolytes; be applied by methods such as PECVD, PVD, CVD, MOCVD, ALD,spin-coating, spray-coating, roller-coating, powder-coating, pyrolysisand/or combinations thereof; have strong adhesion to underlying layerssuch as metals, silicon, glass, oxides, nitrides and/or polymers; havehigh resistance against shrinking or swelling over time and/or in theenvironment used in the ECPR process, for instance in said electrolytes;be non-bleeding, i.e. are not releasing contaminating organic compounds;be sensitive to UV-light; be patterned with said lithography methods; betransparent; and/or be patterned by using said etching methods, forinstance by said dry-etching methods. In some embodiments, saidelastomers can be comprised of Poly-Di-Methyl-Siloxane (PDMS),silicones, epoxy-silicones, fluoro-silicones, fluoro-elastomers,(natural) rubber, neoprene, EPDM, nitrile, acrylate elastomers,polyurethane and/or combinations thereof. In some embodiments, saidelastomer layer can have a tensile elastic modulus (Young's modulus)less than 0.1 GPa, such as less than 1 MPa, for example less than about0.05 MPa. In some embodiments, said elastomer layer can have a hardnessof less than 90 Shore-A, such as less than 30 Shore-A, for example lessthan about 5 Shore-A.

In other embodiments, an insulating layer is applied onto at least someparts of an already patterned surface, for instance a patterned carrier.In an embodiment, the insulating pattern layer is applied with a methodin which the applied materials conformally follow the structures ofunderlying patterned carrier for instance by using methods such asthermal oxidation, thermal nitridation, sputtering, PECVD and/or ALD.Said insulating layer can be patterned in order to uncover at least someparts of said underlying patterned carrier. Said patterning method mayuncover at least some parts of the cavities of said underlying patternedcarrier from the insulating pattern layer. A usable patterning methodincludes that the insulating pattern layer is covering the side-wallsand/or the top of the structures of said patterned carrier while thebottoms of the cavities of said patterned carrier are uncovered in atleast some areas. Said patterning methods can be methods such as saidlithography and/or etching methods described above. In some embodiments,said patterned carrier has at least one layer of insulating material ontop of the patterned structures prior to applying said insulatingpattern layer. For instance, the carrier is patterned by using saidetching methods where the etch-mask comprise at least one layer ofinsulating material and the etch-mask is not stripped prior to applyingsaid insulating pattern layer. This results in a thicker layer ofinsulating material on top of the structures, compared to the bottom, ofsaid patterned carrier. In this embodiment, using etching methods, suchas said dry-etching methods, can uncover the bottom of the cavities ofthe patterned carrier before uncovering the top. Said dry-etching methodmay have a higher etching speed in the direction perpendicular do theplane of said patterned carrier than in lateral direction, known asanisotropic etching, which allows for uncovering the insulating patternmaterial in the bottom of the cavities of the patterned carrier whileleaving the side-walls still covered by the insulating material. Inother embodiments, the insulating pattern layer is patterned in order touncover at least some parts that can be used for electrical connectionto said carrier and/or said conducting electrode layer.

Several embodiments of the master electrode will be described below withreference to the Figures on the drawings.

An embodiment includes supplying a carrier 1 comprising aconducing/semiconducting disc 2 and an insulating coating layer 3. Saidinsulating coating layer 3 may cover all areas of theconducting/semiconducting disc 2 except for an area in the center on theback-side and front-side, as shown in FIG. 1( a). A conducting electrodelayer 4 can be applied onto the front-side of the carrier 1, coveringand being in electrical contact with at least some parts of theconducting/semiconducting disc 2. In one embodiment, said conductingelectrode layer 4 is also covering at least some parts of saidinsulating coating layer 3. In some embodiments, a connection layer 5 isapplied onto at least some parts of said conducting/semiconducting discon the back-side of the carrier in order to enable a good electricalconnection to the master electrode from an external electrical source. Across section of one embodiment of a carrier 1, comprising aconducting/semiconducting disc 2 and an insulating coating layer 3, witha conducting electrode layer 4 and connection layer 5 is illustrated inFIG. 1( b). In an embodiment, an insulating material 6 is applied ontothe carrier 1 and the conducting electrode layer 4 as shown in FIG. 1(c). The insulating material can be patterned using said lithographicaland/or etching methods, forming an insulating pattern layer 7. A crosssection of an embodiment of a master electrode 8 comprising a carrier 1,conducting electrode layer 4, connection layer 5, and insulating patternlayer 7 is illustrated in FIG. 1( d).

In an embodiment, a carrier 1 comprises an insulating disc 9 with aconducting via 11 in the center at least partly filled withconducting/semiconducting material 10, as illustrated in FIG. 2( a). Theinsulating disc 9 may be transparent in order to enable alignmentcapabilities between the master electrode and a substrate. In oneembodiment, a conducting electrode layer 4 is applied onto thefront-side of the carrier 1. In addition, a connection layer 5 can beapplied on the back-side in order to enable a good electrical connectionfrom an external electrical source to the master electrode. Electricconnection between the conducting electrode layer 4 and the connectionlayer 5 is enabled by the via 11. A cross section of one embodiment of acarrier 1, which comprises an insulating disc 9 and a conducting via 11,a conducting electrode layer 4 and a connection layer 5 is illustratedin FIG. 2( b). An insulating material 6 can be applied onto the carrier1 and the conducting electrode layer 4 as shown in FIG. 2( c). Theinsulating material can be patterned using said lithographical and/oretching methods, forming an insulating pattern layer 7. FIG. 2( d)illustrates a cross section of one embodiment of a master electrodecomprising a carrier 1, which comprise an insulating disc 9 and aconducting via 11, a conducting electrode layer 4, a connection layer 5and an insulating pattern layer 7.

Another embodiment includes supplying a carrier 1 comprising aconducting/semiconducting disc 2 which is covered by an insulatingcoating layer 3 on at least some parts, such as on the front-side, ofsaid carrier. In some embodiments, the insulating coating layer isfirstly applied so that it completely covers saidconducting/semiconducting disc, as illustrated in FIG. 3( a). In anembodiment, the insulating coating layer is patterned using saidlithographical and/or etching methods creating an insulating patternlayer 7. In the cavities thus formed, at least some parts of theconducting/semiconducting disc 2 are uncovered, as illustrated in FIG.3( b). The conducting electrode layer 4 can be applied selectively ontothe conducting/semiconducting disc in the bottom of the cavities in theinsulating pattern layer as shown in FIG. 3( c). Some parts, such as thecenter of the back-side, of the insulating pattern layer 7 can beremoved, thereby uncovering the conducting/semiconducting disc 2, inorder to enable an electrical connection to the master electrode. Aconnection layer 5 can be applied on the uncovered area of theconducting/semiconducting disc, such as on the back-side, of the masterelectrode in order to enable a good electrical connection from anexternal electrical source to the master electrode. In some embodiments,some parts of the insulating pattern layer 7 at the backside are removedprior to applying the conducting electrode layer 4. The connection layer5 can then be applied in the same step and with the same method asapplying the conducting electrode layer. However, in some embodimentsthe connection layer 5 can be comprised of at least one layer, appliedin the same step as applying the conducting electrode layer 4, and atleast another conducting layer applied in a subsequent step. FIG. 3( d)illustrates a cross section of a master electrode 8 comprising aconducting/semiconducting disc 2, an insulating pattern layer 7, aconducting electrode layer 4 and a connection layer 5. FIG. 3( e)illustrates a cross section of another embodiment of a master electrode8 comprising a conducting/semiconducting disc 2, an insulating patternlayer 7, a conducting electrode layer 4 and a connection layer 5 wherethe connection layer comprises several layers where at least one is alsocovering some parts of the insulating pattern layer 7 at the backside.

A further embodiment includes supplying a conducting/semiconductingcarrier 1. The carrier is patterned on at least the front-side usingsaid lithographical and/or etching methods. In one embodiment, anetch-mask 12 which is used for patterning the carrier comprises aninsulating material.

A cross section of the patterned conducting/semiconducting carrier 1,with an insulating material as etch-mask 12, is illustrated in FIG. 4(a). An insulating pattern layer 7 can be applied onto said patternedcarrier and onto said etch-mask 12. In some embodiments, the insulatingpattern layer 7 is applied with a method so that it conformally followsthe structures of the underlying pattern layer, as shown in FIG. 4( b).This results in a thicker insulating layer on top of said pattern thanin the bottom of the cavities because of the combination with layer 12.

Said etching methods can be used to uncover the carrier 1 from theinsulating pattern layer 7 in the bottom of the pattern while leavingthe insulating pattern layer 7 on the side walls and on the top.Dry-etching methods can be used that are characterized by having ahigher etch-rate in the bottom of the cavities than on the side walls.In some embodiments, the same amount of insulating material is removedfrom the bottom of the cavities as on the top, leaving an insulatingmaterial thickness on the top corresponding to the thickness of saidetch-mask 12 used for patterning the carrier. FIG. 4( c) illustrates amaster electrode 8 comprising a patterned carrier 1, an etch-mask 12 andan insulating pattern layer 7 that has been etched in order to uncoverthe bottom of the cavities of the patterned carrier.

In some embodiments, a conducting electrode layer is applied selectivelyin the areas on the patterned carrier 1 that is not covered by anetch-mask 12 or an insulating pattern layer 7; and a second etch-mask 12can be applied in the back-side in order to remove the insulatingpattern layer and thereby uncovering some parts of the carrier 1 in asubsequent step, as shown in FIG. 4( d).

Removing parts of the insulating pattern layer 7 at the backside can bedone by using said lithographical, and/or etching methods. A connectionlayer 5 can be applied on the uncovered parts of the carrier in order toenable a good electrical connection from an external electrical sourceto the master electrode. In some embodiments, the electrical connectionin the master electrode is fabricated in the center of the back-side ofthe master electrode. In some embodiments, the connection layer 5 isapplied in the same step as applying the conducting electrode layer 4.In this case, the uncovering of the carrier 1 in the connection area, isdone prior to applying the conducting electrode layer 4. In someembodiments, the connection layer 5 is applied only in the uncoveredparts of the carrier 1. In other embodiments, the connection layer isapplied on the uncovered parts of the carrier and onto some parts of theinsulating pattern layer 7.

FIG. 4( e) illustrates a cross section of one embodiment of a masterelectrode comprising a patterned conducting/semiconducting carrier 1with an insulating etch-mask 12 on top of the carrier structures, aninsulating pattern layer 7, a conducting electrode layer 4 applied inthe cavities of the patterned carrier and a connection layer 5 appliedon the back-side onto some parts of the insulating pattern layer andonto the uncovered parts of the carrier.

In some embodiments, the cavities of the master electrode (8) can bemade deeper, prior to applying the conducting electrode layer 4, byremoving material from the carrier 1 in the bottom of the cavities ofthe insulating pattern layer 7, for instance by using said etchingmethods. In some embodiments, dry-etching methods can be used. For someembodiments, said insulating pattern layer 7 can be used as anetch-mask. Creating deeper cavities results in that the master electrodecavities can be filled with a larger amount of predeposited materialused for ECPR plating and/or by etched material during ECPR etching.FIG. 5 illustrates a cross section of a master electrode 8 where thecavities of the insulating pattern layer 7 have been etched deeper intothe carrier 1 which thereafter has been covered by a selectivelydeposited conducting electrode layer 4.

One embodiment includes forming said insulating pattern layer 7 ontosaid carrier 1 by bonding and patterning an insulating bond-layer 13. Insome embodiments, the carrier 1 comprises a conducting/semiconductingdisc 2 covered with an insulating coating layer 3 except for in thecenter of the front- and back-side of the carrier. In other embodiments,the carrier comprises an insulating disc 9 with a conducting via 11 inthe center of the carrier 1.

In some embodiments a conducting electrode layer 4 has been applied ontothe carrier prior to applying the insulating bond-layer 13. In someembodiments, the insulating bond-layer is adhered to a bond-carrier 14that can be removed after the insulating bond-layer 13 has been appliedonto the carrier 1. For instance, the insulating bond-layer 13 can beSiO₂ on a Si bond-carrier 14 or the insulating bond-layer 13 can beglass, such as quartz, or a polymer film on any removable bond-carrier14. In some embodiments, an adhesive bond-layer 15 can be applied ontothe insulating bond-layer 13 prior to bonding it to the carrier 1 inorder to improve bonding properties such as adhesive strength. Theadhesive bond-layer 15 can be of a material that gives goodbond-properties together with the carrier and/or with the conductingelectrode layer 4 on the carrier 1 and should be of a conductingmaterial. Alternatively, the adhesive bond-layer 15 can be of anon-conducting material and be selectively removed by etching. Forinstance, the adhesive bond-layer 15 may comprise a metal and/or analloy that bonds well with the conducting electrode layer 4. Theadhesive bond-layer can comprise materials such as mentioned for saidconducting electrode layer 4.

A cross section of a carrier 1 with a conducting electrode layer 4 and abond-carrier 14 with an insulating bond-layer 13 and an adhesivebond-layer 15 prior to bonding is illustrated in FIG. 6( a).

FIG. 6( b) illustrates how an insulating bond-layer 13 on a bond-carrier14 is bonded to a carrier 1 with a conducting electrode layer 4 and anadhesive bond-layer 15 in-between. In some embodiments, the layersin-between the insulating bond-layer 13 and the carrier 1 are altered(e.g. mixed) during the bonding process and a bond-intermediate layer 16is formed. The bond-carrier 14 can be removed mechanically and/or byusing said etching methods, such as dry-etching or wet-etching. Afterthe bond-carrier 14 has been removed, the insulating bond-layer 13 canbe patterned using said lithographical and/or etching methods. FIG. 6(c) illustrates a cross section of one embodiment of a master electrode 8comprising a patterned insulating bond-layer 13 that has been bonded toa carrier 1 with a bond-intermediate layer 16 in between which iscomprising a conducting electrode layer 4 and an adhesive bond-layer 15.In some embodiments, a conducting electrode layer 4 can be appliedselectively into the cavities of the patterned insulating bond-layer 13onto said bond-intermediate layer 16 or onto said carrier 1 if nobond-intermediate layer 16 exists (i.e. when the insulating bond-layer13 is applied directly onto the carrier 1).

In an embodiment, the master electrode enables an electrical connectionfrom an external electrical source to at least some parts of saidconducting electrode layer.

In some embodiments, the electrical connection in made from an externalelectrical source to said conducting/semiconducting material of saidcarrier which is connected to at least some parts of the conductingelectrode layer.

In an embodiment, the electrical connection is made from an externalelectrical source to a connection layer which is connected to at leastsome parts of the conducting/semiconducting parts of the carrier whichin turn is connected to the conducting electrode layer.

The electrical connection can for instance be located on the back-sideof said carrier, i.e. the opposite side of the insulating structures ofthe master electrode. In some embodiments, the electrical connection canbe used in the center of the back-side of said carrier. In anotherembodiment, the electrical connection is made from front-side, such asin the perimeter of said carrier.

In some embodiments, the insulating parts of said carrier and/or theinsulating pattern layer have been applied in a way that there will beno significant electrical connection and/or no short circuit between theelectrical connection to the conducting electrode layer and theelectrical connection to the substrate, either directly and/or throughthe electrolyte, except for in the electrolyte filled cavities definedby the insulating pattern layer and the substrate during ECPR etching orECPR plating. For instance, insulating material is covering allconducting/semiconducting parts of the carrier except for in thecavities of the insulating pattern layer and in an electrical connectionarea.

In some embodiments, the master electrode is characterized by allowingfor creating an electrical connection from an external electrical sourceto a substrate seed layer when the master electrode is put in contactwith the substrate during ECPR etching or plating.

In some embodiments, at least some areas of said seed layer, which canbe used for electrical contact, is not covered by the master electrodeduring physical contact with the substrate.

In some embodiments, an electrical contact to the substrate seed layercan be supplied by having a master electrode with an area that entersinto physical contact with a larger substrate seed layer area.

FIG. 7( a) illustrates a cross section of a master electrode 8 withsmaller area that enters into contact with a large substrate 17 seedlayer 18 area.

FIG. 7( b) illustrates a top view of one embodiment of a masterelectrode with smaller area that enters into contact with a largersubstrate seed layer 18 area.

In some embodiments, the master electrode and the substrate have thesame dimensions and material has been removed from the master electrodein at least some areas in order to give place for an electricalconnection to the seed layer on the substrate. In one embodiment, arecess is arranged in the perimeter of the master electrode which allowsfor a connection to the seed layer of the substrate.

FIG. 7( c) illustrates a cross section of a master electrode 8 with arecess 19 that allows for electrical connection to the substrate seedlayer. Said recess can be present all around the circumference of themaster electrode or in a few specific connection sites.

In some embodiments, connection holes 20 can be made through the masterelectrode 8 allowing for electrical connection to the seed layer 17 ofthe substrate 17. In one embodiment, the connection holes 20 are madeadjacent the perimeter of the master electrode 8.

FIG. 7( d) illustrates a top view of the front-side of a masterelectrode 8, comprising an insulating pattern layer 7 and a conductingelectrode layer 4, with connection holes 20 in the perimeter. In oneembodiment, the connection holes 20 are made inside the master electrode8 area, as illustrated in a top view in FIG. 7( e). Said recess and/orconnection sites can be created by methods such as said lithographicaland/or etching methods and/or with mechanical methods such as polishing,grinding, drilling, ablation, CNC-machining, ultra-sonic machining,diamond machining, waterjet machining, laser machining, (sand or fluid)blasting, and/or by combinations thereof. The recess and/or connectionsites may be dimensioned to fit electrical contacts. An electricalcontact can for instance be a thin foil, springs, pins and/or othersuitable electrical contacts and/or by a combination thereof. Theelectrical contact can comprise at least one layer of material that doesnot erode or oxidize during the ECPR etching and/or plating processand/or in the electrolytes used therefore, for instance: stainlesssteel, Au, Ag, Cu, Pd, Pt, platinized titanium and/or by combinationsthereof.

In some embodiments, the connection sites to the seed layer, provided bythe master electrode design, are located in a way that it enables auniform current distribution in the seed layer during ECPR etchingand/or plating. For instance, a recess can be located all along theperimeter of the master electrode which allows for a continuouselectrical connection to the seed layer perimeter. In anotherembodiment, a number of (such as at least three) connection holes can bedistributed evenly along the perimeter of the master electrode, whichenables that a well distributed electrical connection can be achieved tothe seed layer of the substrate.

In some embodiments, the parts of the master electrode that areconducting and connected to the conducting electrode layer and arelocated in contact with and/or in close proximity of the electricalconnection to the seed layer, are coated with and insulating material inorder to prevent a short circuit from the conducting electrode layer ofthe master electrode to the substrate seed layer during ECPR etchingand/or ECPR plating.

In some embodiments, an electrical seed layer connection is anintegrated part of the master electrode. In this case, the seed layerconnection on the master electrode must be isolated from the conductingparts of the master electrode that are connected to the conductingelectrode layer. Otherwise there could be a short circuit between thetwo electrodes when the master electrode is used for ECPR etching orplating. In some embodiments, the electrical connection to theconducting electrode layer of the master electrode is made in the centerof the back-side of said carrier where the insulating coating of thecarrier has been removed. In this case, the seed layer connection can bea conducting layer from the back-side perimeter to the front-side,separated from the conducting parts of the carrier by an insulatingmaterial. Said seed layer connection can comprise the same materials andcan be applied with the same methods as used for said conductingelectrode layer described above.

FIG. 7( f) illustrates a master electrode 8 comprising a conductingcarrier, an insulating pattern layer 7 and a conducting electrode layer4. Said insulating pattern layer is covering all areas of the conductingcarrier except for in the cavities on the front side and in the centerof the back-side, in which an electrical connection is enabled through aconnection layer 5. Said seed layer connection 31 is provided on theperimeter on the back-side, the edge, and the perimeter on the frontside of the master electrode. The seed layer connection 31 is isolatedfrom the other conducting parts of the master electrode by theinsulating pattern layer. An insulating layer may be arranged at thelateral sides of the seed layer connection.

FIG. 7( g) illustrates how the master electrode 8 comprising aninsulating pattern layer 7, a conducting carrier 1, a conductingelectrode layer 4, a connection layer 5 and a seed layer connection 31is put in contact with a substrate 17 with a seed layer 18. Anelectrolyte 29 is enclosed in the electrochemical cells defined by thecavities between the insulating patter layer and the seed layer. Anexternal electrical voltage source is connected to the connection layer5 (said connection layer being electrically connected to said conductingelectrode layer 4 through said carrier 1) and to the seed layerconnection 31 (said seed layer connection being electrically connectedto said seed layer) whereby an anode material, which is predeposited onsaid conducting electrode layer, which is anode, in the cavities of theinsulating pattern layer, is dissolved and transported through saidelectrolyte and plated structures 24 are formed onto the seed layer,which is cathode, inside said electrochemical cells. By reversing thepolarity of the electric voltage source, electrochemical etching of theseed layer takes place.

FIG. 7( h) illustrates how the seed layer connection 31 is arranged overa large surface of the pattern layer 7 and substantially over the entiresurface, except adjacent the edges to the cavities of the pattern layer.The separate seed layer connection portions 31 shown in FIG. 7( h) areinterconnected at other positions not shown in FIG. 7( h) because thesurface of the pattern layer may form a continuous surface.

If the surface of the pattern layer does not form a continuous surface,the different portions 31 of the connection can be connected withconnection areas at the backside of the carrier through the carrier asshown in FIG. 7( i). Otherwise, the seed layer contacted by the separateconnection portions 31 may form a connection between the separateconnection portions 31. The separate connection portions 31 cancontribute to decreasing the resistance of the seed layer, especially atthin seed layers. Less resistance may have advantages as describedfurther below.

In some embodiments, said recess (see FIG. 7( d)) is created in theperimeter of a carrier used for the master electrode in order to improvesome methods for applying an insulating pattern layer to said carrier.For instance, when an insulating pattern layer is fabricated byspin-coating or spray-coating the carrier with a polymer (e.g. aphotoresist) an edge-bead of insulating material may be formed in theperimeter of the carrier because of the application process. By creatinga recess in the carrier prior to applying an insulating pattern layerusing spin-coating or spray-coating the edge-bead effect can be reducedor even eliminated. By reducing or eliminating the edge-bead, a moreplanar surface can be achieved on the master electrode which improvesthe physical contact between the master electrode and the substrateduring ECPR etching and/or ECPR plating. The edge-bead effect is muchdepending on the character of the recess used for the carrier. Differentembodiments of recessed carriers for the master electrode areillustrated in FIGS. 8( a) to 8(h).

FIG. 9( a) illustrates how and edge-bead 21 has been formed in theinsulating pattern layer 7 when using a carrier 1 without any recess.FIG. 9( b) illustrates how the edge-bead 21 in the insulating patternlayer 7 is reduced when using a carrier with a recess using one of theembodiments illustrated in FIG. 8. Any and all of the embodiments, inFIGS. 8( a) to 8(h) can be used in order to reduce the edge-bead 21 ofan insulating pattern layer 7.

In some embodiments, the edge-bead 21 can be reduced by using aspin-carrier 22 when applying the insulating pattern layer 7 byspin-coating. The method for using a spin-carrier 22 is characterized bythe spin-carrier 22 having a recess in which the master electrodecarrier 1 is embedded, as shown in FIG. 10( a). The height of the recessin the spin-carrier may be the same as the thickness of the carrier ofthe master electrode. The gap between the edge of the carrier of themaster electrode and the side wall spin-carrier's cavity is made assmall as possible. The carrier 1 can be attached to the spin-carrier forinstance with an adhesion layer and/or by applying vacuum through one orseveral vacuum-grooves that have been fabricated in the spin-carrier.

When applying the insulating pattern layer 7 by spin-coating using saidspin-carrier 22, the edge-bead 21 of the insulating pattern layer 6 willappear in the perimeter of the spin-carrier 22 instead of in theperimeter of the master electrode carrier 1, which is illustrated inFIG. 10( b). FIG. 10( c) illustrates the master electrode 8 afterseparating it from the spin-carrier 22 and after patterning theinsulating pattern layer 7.

In some embodiments, said edge-bead 21 in the insulating pattern layer7, illustrated in FIG. 11( a), can be removed by using edge-beadremoving methods such as dissolving in organic solvents, mechanicalremoving and/or by removing insulating pattern layer edge-bead area bysaid lithographical and/or etching methods. FIG. 11( b) illustrates amaster electrode 8 were the edge-bead 21 in the insulating pattern layer7 has been removed by using said edge-bead removing methods.

In some embodiments, during the fabrication of the master electrode 8,the electrical resistance of the conducting/semiconducting parts of thecarrier 1 and the conducting electrode layer 4 may be matched to theresistance of the seed layer 17 on a substrate 17 on which ECPR etchingand/or plating is performed. The resistance of the carrier 1 and/orconducting electrode layer 4 can be decreased or increased by choosingmaterials with lower or higher resistivity respectively and/or by makingthe carrier 1 and/or the conducting electrode layer 4 thicker or thinnerrespectively. The total resistance for an electrical current during ECPRetching and/or plating is determined by the sum of the resistance of thefollowing pathes:

-   -   1. the conducting/semiconducting parts of the carrier 1,    -   2. the conducting electrode layer 4,    -   3. electrochemical cells 23 formed in ECPR etching and/or        plating and    -   4. the seed layer of the substrate (18)

For convenience, the resistance of a path through saidconducting/semiconducting parts of said carrier 1 is called R₁; theresistance of a path through said conducting electrode layer 4 is calledR₄; the resistance of a path through the seed layer 18 is called R₁₈;and the resistance of a path through said electrochemical cells 23formed in ECPR etching and/or plating is called R₂₃.

In some embodiments, the carrier 1 and the conducting electrode layer 4of the master electrode 8 are characterized in that a current suppliedduring ECPR etching and/or plating will experience the same totalresistance when passing through the carrier 1, conducting electrodelayer 4 and the seed layer 18, independently on in which area it passesthe electrochemical cells 23. In some embodiments, this is done bysupplying an electrical contact from an external power supply only tothe center of the back-side of the carrier 1 and to the perimeter of theseed layer 18 on the substrate 17. In this case, if the total electricalresistance for a current passing from the center of the back-side of thecarrier 1, through the said carrier, conducting electrode layer 4 andthe seed layer 18 to the electrical contacts at the perimeter is thesame independent on in which area it passes through the electrochemicalcells 23, the current density that passes during ECPR etching and/orplating will be the same independent on the location of theelectrochemical cells with respect to the seed layer electricalcontacts. Thereby, the etching and/or plating rate, which is linearlyproportional to the current density, will be the same in allelectrochemical cells 23, independent on the location. The describedmaster electrode/seed layer resistance matching reduces or eveneliminates a problem of radial dependent non-uniformal etching/platingrates, resulting in non-uniform radial height distribution, inherentlyassociated with conventional electrodeposition/electrochemical etchingmethods; said problems being described as the terminal effect.

In some embodiments, such as at thin seed layer, the total resistance ofthe carrier 1 and conducting electrode layer 4 is lower than theresistance of the seed layer 18, causing the current density to becomehigher in the electrochemical cells 23 that are located closer to theperimeter than in the center of the substrate and master electrode whenperforming ECPR etching and/or plating. In other embodiments, such as atthick seed layer, the total resistance of the carrier 1 and conductingelectrode layer 4 is higher than the resistance of the seed layer 18,causing the current density to become lower in the electrochemical cells23 that are located closer to the perimeter than in the center of thesubstrate 17 and master electrode 8 when performing ECPR etching and/orECPR plating.

For instance, a resistance R′ of the path to and from theelectrochemical cells 23 in the center can be matched to the resistanceR″ of the path to and from the electrochemical cells in the perimeter,illustrated in FIG. 12( a), so that:

1. if R′=1/(1/R₁′+1/R₄′)+R₁₈′ is equal to R″=1/(1/R₁″+1/R₄″)+R₁₈″, thenj′=j″; or

2. if R′=1/(1/R₁′+1/R₄′)+R₁₈′ is greater than R″=1/(1/R₁″+1/R₄″)+R₁₈″+,then j′<j″; or

3. if R′=1/(1/R₁′+1/R₄′)+R₁₈′ is less than R″=1/(1/R₁″+1/R₄″)+R₁₈″, thenj′>j″,

where j′ is the current density in the electrochemical cells in thecenter and j″ is the current density in the electrochemical cells in theperimeter.

By matching the resistances R₁ and R₄ to R₁₈ in different ways, aspecific height distribution of ECPR etched or plated structures along aradial direction from the center to the perimeter of the masterelectrode can be achieved.

More specifically, in some embodiments, the matching of the resistancesin the master electrode to the resistance in the seed layer is done byadjusting the thickness of the layers to the resistivity of thematerials. In an embodiment, the thicknesses and the resistivity of thecarrier 1 and the conducting electrode 4 are matched to that of the seedlayer, so that R₁+R₄=R₁₈ which gives a uniformly distributed currentdensity (i.e. plating or etching rate) in radial direction. FIG. 12( b)illustrates the radial heights distribution in of ECPR etched or platedstructures (24).

In another embodiment, the thicknesses and the resistivity of thecarrier 1 and the conducting electrode 4 are matched to that of the seedlayer, so that R₁+R₄<R₁₈ which gives a higher current density in theareas located closer to the center and to the perimeter. FIG. 12( c)illustrates the radial heights distribution in of ECPR etched or platedstructures 24.

In a further embodiment, the thicknesses and the resistivity of thecarrier 1 and the conducting electrode 4 are matched to that of the seedlayer so that R₁+R₄>R₁₈ which gives a higher current density in theareas located closer to the center and to the perimeter. FIG. 12( d)illustrates the radial heights distribution in of ECPR etched or platedstructures 24.

In some embodiments, the conducting parts (for instance aconducting/semiconducting disc 2) of the carrier 1 is only connected tothe conducting electrode layer 4 in the center on the front-side due toan insulating material coating 3 as illustrated in FIG. 1( d). In thiscase, it is only the resistivity and thickness of the conductingelectrode layer 4 that needs to be matched with a seed layer 18.

In some embodiments, a radial depending height distribution of ECPRetched or plated structures can be used to compensate a different heightdistribution that comes from a previous or subsequent process step. Inone embodiment, the resistance in the master is matched to a seed layer18, which is applied with a uniform thickness (for instance by PVD) ontoa substrate 17 with a concave layer 25 illustrated in FIG. 13( a), sothat 1/R₁+1/R₄<1/R₁₈, and ECPR etched or plated structures 24 isfabricated with a convex radial height distribution that compensates forthe concave layer so that the top of said ECPR etched or platedstructures 24 end up at the same height h from the substrate, asillustrated on FIG. 13( b). In another embodiment, the resistance in themaster is matched to a seed layer 18, which is applied with a uniformthickness (for instance by PVD) onto a substrate 17 with a convex layer26 illustrated in FIG. 14( a), so that 1/R₁+1/R₄>1/R₁₈, and ECPR etchedor plated structures 24 is fabricated with a concave radial heightdistribution that compensates for the convex layer so that the top ofsaid ECPR etched or plated structures 24 end up at the same height hfrom the substrate, as illustrated on FIG. 14( b).

The method for matching the resistance in the master electrode to theseed layer is in no way limited to the master electrode embodimentillustrated in FIG. 12, and it can be used for all embodiments of masterelectrodes.

In order to achieve certain plating or etching effects, the masterelectrode may be arranged with a disc and electrode layer havingdifferent thicknesses from the centrum and/or having different materialsfrom the centrum; said different materials having different resistivity.For example, the thickness may be halved or alternatively theresistivity may be doubled at half the radial distance from the centrum.If the inner half is adapted to the seed layer resistance, thestructures in the corresponding area will have a uniform height, whilethe structure corresponding to the outer half will have a decreasingheight. Further designs are possible.

In some embodiments, alignment marks can be fabricated in at least someparts of the master electrode in order to be able to align the masterelectrode to a substrate used in ECPR etching and/or plating. In someembodiments, said alignment marks comprise structures and/or cavities onthe master electrode. The structures and/or cavities can be manufactureswith said lithographical and/or etching methods. The material for thealignment marks can be the same as can be used for said carrier, saidconducting electrode layer and/or said insulating pattern layer. Thealignment marks can be located on said carrier, on said conductingelectrode layer and/or on said insulating pattern layer. In someembodiments, the alignment marks can be a part of the structures orcavities of the insulating pattern layer. In some embodiments, thealignment marks can be manufactured in the same step as uncovering someparts of said insulating coating layer on the back-side of said carrier.In an embodiment, the master electrode comprises a carrier, which istransparent in the light used for alignment (e.g. ultra-violet light,visual light, infra-red light and/or X-rays), a conducting electrodelayer and an insulating pattern layer which comprise said alignmentmarks. If the conducting electrode layer is not transparent to the lightused for alignment, there can be openings in the conducting electrodelayer where the alignment marks are/or shall be placed, so that it willbe possible for the light used for alignment to pass through the masterelectrode where the openings are. The openings can be produced when thecarrier is being covered by the conducting electrode layer (e.g. bycovering the specific area during the deposition process). The openingscan also be produced after the conducting electrode layer has beenapplied (e.g. using said mechanical, lithographical and/or etchingmethods). In some embodiments, the alignment structures are made of atransparent material which will make it easier to align through themaster when aligning against the substrate. Alternatively, the alignmentmarks is fabricated in the conducting electrode layer and/or carrier. Ifthe insulating pattern layer is non-transparent, openings can be made inthe insulating pattern layer in the areas of alignment marks using saidlithographical and/or etching methods. Said openings in the insulatingpattern layer are in some embodiments fabricated when patterning saidinsulating pattern layer. In some embodiments, said alignment markscomprise a material which is non-transparent and can be located onto aportion of otherwise transparent materials, such as a metal onto quartz,in this way enabling a good contrast of the alignment marks. In someembodiments, the master electrode comprises a non-transparent carrierwith alignment marks on the back-side, a conducting electrode layer andan insulating pattern layer. The structures of the insulating patternlayer on the front-side of the master electrode can then be alignedrelative to the alignment marks on the back side. Alternatively, thealignment marks are fabricated after making the insulating pattern layerand the alignment marks on the back-side are aligned relative to theinsulating pattern on the front-side. In some embodiment, the alignmentstructures are a part of the insulating pattern layer and/or conductingelectrode layer even if the master electrode comprises a non-transparentcarrier, for instance when using a face-to-face alignment method. Insome embodiments such as when using a non-transparent carrier, alignmentmarks can be fabricated in the conducting electrode layer and/orinsulating pattern layer on the front-side of the master electrode; andthrough holes can be made in the carrier, using said lithographical andetching methods, in the areas of the alignment marks thereby making saidalignment marks visible also from the back-side which allows for the useof back-side alignment methods. In one embodiment, said through holescan be fabricated after forming the conducting electrode layer andinsulating pattern layer and in some cases said through holes can befilled with an transparent material. In other cases, said through holesare fabricated prior to forming said conducting electrode layer andinsulating pattern layer, such as when firstly filling said throughholes with a transparent material.

In some embodiments, aligning methods can include a calibrationprocedure characterized by measuring the overlay error of ECPR etched orplated structure layers formed with a certain master electrode and thencompensating for said error when using said master electrode insubsequent ECPR etching or plating steps. This can be useful forinstance when having back-side alignment keys on the master electrode.

In some embodiments, the insulating pattern layer can be fabricated witha pattern that compensates for or is adapted to the topography on thesubstrate used in ECPR etching and/or ECPR plating.

In some embodiments, this can be done using a master electrode having aninsulating pattern layer with at least one cavity in the areacorresponding to the area with topography on the substrate when themaster electrode and substrate are put in close contact when performingECPR etching and/or plating. In some embodiments, the cavities made tocompensate for topography on the substrate do not have be as deep as therest of the cavities of the insulating pattern layer. If the cavitiesaround the topography do not reach the conducting electrode layer of themaster electrode, no ECPR etching and/or plating will occur in thisspecific area, which can be used in some embodiments. In someembodiments, the insulating pattern layer can be fabricated withstructures of different heights by patterning the insulating layer morethan once. Some of the topography of the substrate may be free fromelectrically conducting material, such as seed layer.

In one embodiment, firstly the insulating pattern layer is formed usingsaid lithographical and/or etching methods, creating cavities reachingdown to the carrier or conducting electrode and secondly the insulatingpattern layer is patterned once more in at least some areas, creatingcavities that compensate for topography on the substrate but do notreach the carrier or conducting electrode layer.

FIG. 15( a) illustrates how an etch-mask 12 is applied and patterned ontop of an insulating pattern layer 6 on a carrier using saidlithographical methods.

FIG. 15( b) illustrates how cavities, that reach down to the underlyingcarrier 1, are etched into said insulating pattern layer in the areasthat are not protected by said etch-mask 12 using said etching methods.

FIG. 15( c) illustrates how the first etch-mask is removed, a secondetch-mask 12 is applied and patterned onto some parts of the previouslyetched insulating pattern layer 6 using said lithography methods.Alternatively, the first etch-mask is patterned a second time instead ofremoving the first etch-mask and applying and patterning a secondetch-mask.

FIG. 15( d) illustrates how a second layer of cavities, that cancompensate for topography on a substrate, are etched into the insulatingpattern layer using said etching methods in the areas that are notprotected by the etch-mask 12. FIG. 15( e) illustrates the finishing ofa master electrode 8 after said etch-mask has been removed and after aconducting electrode layer 4 is applied onto said carrier in thecavities of the insulating pattern layer. The top layer of cavities cancompensate for topography in a substrate and the bottom layer ofcavities, reaching down to the conducting electrode layer, can be usedfor forming ECPR etched or plated structures.

In another embodiment, firstly the insulating pattern layer is patternedusing said lithographical and/or etching methods creating cavities thatcompensate for topography on the substrate but do not reach the carrieror conducting electrode layer below and secondly the insulating patternlayer is patterned once more to create the cavities that reach thecarrier or conducting electrode layer below.

FIG. 16( a) illustrates how an etch-mask 12 is applied and patternedusing said lithography methods; and how cavities in the insulatingpattern layer 6 is etched in the areas that are not protected by saidetch-mask. These firstly created cavities can compensate for topographyon a substrate and are not reaching down to the underlying carrier 1.

FIG. 16( b) illustrates how the first etch-mask is removed and how asecond etch-mask 12 is applied and patterned using said lithographicalmethods thereby only covering the areas on the insulating pattern layer6 that is not intended to be etched down to the carrier 1 in asubsequent step.

FIG. 16( c) illustrates the finishing of a master electrode 8 bycreating cavities in the insulating pattern layer 6 by etching down tothe carrier 1 in the areas not protected by said second etch-mask 12;and by removing said etch-mask; and applying a conducing electrode layer4 in onto said carrier in the cavities of the insulating pattern layer.The firstly formed cavities of the insulating pattern layer cancompensate for topography on a substrate.

In some embodiments, forming a master electrode with an insulatingpatter layer that can compensate for topography on a substrate includesapplying multiple layers of insulating material and at least oneetch-stop layer, said etch-stop layer being arranged between twoinsulating pattern layers. Said etch-stop layer can comprise materialsmentioned above, such as SiN or SiO₂ and can be applied with methodsmentioned above, such as PVD, CVD or PECVD. This embodiment includesfirstly etching down cavities in a top insulating pattern layer down tothe etch-stop layer; removing (i.e. patterning) portions of theetch-stop layer using said lithographical and etching methods; andetching another layer of cavities in the bottom insulating pattern layerusing said patterned etch-stop layer as an etch-mask down to anunderlying etch-stop layer, carrier or conducting electrode layer. Thesequence can be repeated multiple times in order to create a masterelectrode with an insulating pattern layer with multiple layers ofcavities.

FIG. 17( a) illustrates how two insulating pattern layers 7 are applied,with an etch-stop layer 27 arranged between, onto a carrier 1; and howan etch-mask 12 is applied and patterned onto the top insulating patternlayer.

FIG. 17( b) illustrates how portions of the top insulating pattern layer7 are etched in the areas that are not protected by said etch-mask 12forming a top layer of cavities. The etching is stopped when the toplayer cavities reach down to said etch-stop layer 27.

FIG. 17( c) illustrates how portions of said etch-stop layer 27 isremoved by methods such as said lithographical and etching methods,thereby uncovering at least some portions of the underlying insulatingpattern layer 7.

FIG. 17( d) illustrates how portion of the bottom insulating patternlayer 7 are etched in the areas that are not protected by said patternedetch-stop layer 27 forming a bottom layer of cavities, said cavitiesreaching down to the underlying carrier 1.

FIG. 17( e) illustrates the finishing of a master electrode 8 byremoving said etch-mask 12; and removing the portions of said patternedetch-stop layer 27 that are not protected by the top insulating patternlayer 6; and applying a conducting electrode layer 4 onto said carrier 1in the cavities of the bottom insulating pattern layer.

In one embodiment, cavities in the insulating pattern layer are firstlycreated as an imprint of a substrate template having the same topographyas the substrate surface and secondly said insulating pattern layer ispatterned, creating cavities down to the underlying carrier orconducting electrode layer.

FIG. 18( a) illustrates how a substrate template 30 is forced against aninsulating pattern layer 7 on a carrier 1, thereby creating cavities insaid insulating pattern layer which are an imprint of the protrudingparts of the substrate template.

FIG. 18( b) illustrates how cavities has been created in said insulatingpattern layer 7 on a carrier 1 after removing said substrate template30.

FIG. 18( c) illustrates the finishing of a master electrode 8 bypatterning said insulating pattern layer 6, into which firstly animprint of a substrate template has been formed, down to said carrier 1by using said lithography and etching methods; and by applying aconducting electrode layer 4 onto said carrier in the bottom of thecavities of the insulating pattern layer.In some embodiments, forming a master electrode comprising an insulatingpattern layer that can compensate for topography on a substrate caninclude: applying a layer of negative photoresist and/or a UV-curingpolymer, using the above mentioned methods for applying an insulatingpattern layer; exposing said layer to UV-light through a photomask;applying a second layer of photoresist and/or a UV-curing polymer;exposing said second layer to UV-light through a second photomask; andif necessary, performing an post-exposure-bake (PEB) step prior todeveloping both layers simultaneously. In some embodiments, a hard bakeis performed in order to improve adhesion between said layers as well asmechanical and chemical properties. Two or more patterned layers may befabricated on top of each other using this concept.Alternatively, direct write methods such as laser-beam or E-beamexposure may be used instead of exposing said layers with UV-lightthrough a photomask.

FIG. 19( a) illustrates how the master electrode 8 with a predepositedanode material 28 is put into contact with a substrate 17 with a seedlayer 18 enclosing electrolyte 29 in the cavities of the insulatingpattern layer 6 in order to form plated structures 24 and how theinsulating pattern layer is compensating for topography 30 on thesubstrate.

FIG. 19( b) illustrates the substrate 17 with topography 30 afterremoving the master electrode and how plated structures 24 have beenformed and after removing the seed layer 18 in the areas between thestructures.

In some embodiments, the insulating pattern in the master electrode canbe fabricated so that it is possible to form etched or plated structuresthat are continuous across a topography portion on a substrate (i.e. notonly on top of or adjacent to the substrate topography).

FIG. 20( a) illustrates a master electrode 8 comprising an insulatingpattern layer 7 with a top layer of cavities that compensates fortopography 30 on a substrate 17 and a seed layer 18. The insulatingpattern layer also comprises a bottom layer of cavities reaching down toa conducting electrode layer 4 on a carrier 1. An anode material 28 ispredeposited onto the conducting electrode layer.

FIG. 20( b) illustrates said master electrode 8 and a substrate 17; saidmaster electrode having an insulating pattern layer 7 that compensatefor topography 30 on said substrate; said substrate having a seed layer18 applied onto the top surface.

FIG. 20( c) illustrates how the master electrode 8 is put into contactwith a substrate 17 with a seed layer 18 enclosing electrolyte 29 in thecavities of the insulating pattern layer 7 where plated structures 24 onthe substrate is formed. The insulating pattern layer 7 also hascavities that compensate for the topography 30 on the substrate.

FIG. 20( d) illustrates how plated structures are formed onto asubstrate 17 with topography 30 after the master electrode 8 is removedand after the seed layer 18 is removed in the areas that are not coveredby the plated structures.

In some embodiments, an etching pattern is created with anelectrochemical process by using the conducting electrode layer of themaster electrode as cathode whereby material is dissolved from thesubstrate, transferred in the electrolyte and deposited on the cathodethereby creating ECPR etched structures on the substrate correspondingto the pattern of insulating pattern layer on the master electrode.Since the material that is being dissolved from the substrate, which isanode, also is deposited at the conducting electrode layer, which iscathode, the amount of dissolved anode material in the electrolyteremains close to constant during the electrochemical process. If thedeposition rate of the dissolved material is zero, the concentration ofdissolved anode material ions in the electrolyte increases quickly, thisslows down the electrochemical reaction until it eventually stops. A toohigh ion concentration can also result in precipitation of salts. Inthis case, only small amounts could be dissolved from the substrate andonly thin layers could be patterned. Instead, by making sure that thedissolution reaction has an appropriate deposition reaction, thickerlayers substrate can be etched. The dissolution and deposition reactionin the electrochemical process is determined by the thermodynamic andkinetic reaction at a given applied potential in a specific system ofanode, cathode and electrolyte. By choosing the appropriate anodematerial, cathode material and electrolyte, the desired dissolution anddeposition reaction can be achieved since they are thermodynamically andkinetically favorable in the chosen system.

One example of appropriate anode, cathode and electrolyte system is Nias anode material, Au as a cathode material and a Watt's bath used aselectrolyte. In some aspects, the deposition reaction does not have tobe corresponding to the dissolution reaction exactly. As long as thedeposition rate of the dissolved material is larger than zero, thebuildup of ion concentration of anode material in the electrolyte willbe slow which means that it will take longer time before the reactionstops and hence thicker layers on the substrate can be etched. Forinstance, the deposition rate of the dissolved ions can be 90-100% ofthe dissolution rate. In this example, the ion concentration ofdissolved anode will increase slowly, but in some aspects a desiredetched thickness can be achieved before the concentration becomes toohigh. In some cases, the dissolution rate can be lower than thedeposition speed which eventually leads to depletion of ionconcentration in the electrolyte. However, if the dissolution reactionis not too low compared to the deposition reaction (e.g. >90% of thedeposition rate), a desired thickness can still be etched from thesubstrate before depletion of anode material ions in the electrolyte.One example of an inappropriate system is Ag as anode material, Al ascathode material and an alkaline silver cyanide bath as an electrolyte.In this example, the deposition rate of silver ions is zero which willlead to a fast buildup of silver ions in the electrolyte.

A plating pattern is created by an electrochemical process by using theconducting electrode layer of the master electrode as anode and havingpredeposited anode material on the anode inside the cavities defined bythe master electrode whereby said anode material is dissolved,transferred in the electrolyte and deposited on the substrate, beingcathode, thereby creating ECPR plated structures on the substratecorresponding to the cavities of the insulating pattern layer on themaster electrode.

One problem with prior art processes which do not have a predepositedmaterial is that anode material is dissolved directly from conductingelectrode layer 4 in the master, the master electrode will eventuallywear out since the dissolved material is undercutting the insulatingpattern layer 7, as illustrated in FIG. 23( a). By having a predepositedanode material 28 in the cavities of the master electrode 8, it ispossible to have a conducting electrode layer 4 comprising an inertmaterial that does not dissolve during the electrochemical process andno undercutting of the insulating pattern layer 7 occurs, as illustratedin FIG. 23( b). Thereby, the master electrode can be resused a largenumber of times which leads to a more cost and time efficient patterningprocess.

Another problem with prior art processes, which do not have predepositedmaterial is that the dissolved material that is undercutting theinsulating pattern layer leads to that the anode area increasesdifferently in large contra small cavities in the insulating patternlayer. In large cavities, the area increase due to undercutting issmaller than in small cavities, as illustrated in FIG. 23( a).Increasing the anode area leads to a higher current density (i.e.plating rate) at the cathode. Hence, the structures plated in the smallcavities of the insulating pattern layer will be deposited with a higherplating rate than the structures in the large cavities leading to anuneven thickness distribution that depends on the pattern. Also thisproblem is solved by having a predeposited material, since no areaincrease will occur and thereby the current density (plating rate) willbe the same in all cavities, non-depending on the size of the patterns.

Also, the dissolution of predeposited material prevents the depletion ofthe concentration of ions in the electrolyte that are deposited on thecathode. A depletion of ions in the electrolyte would gradually slowdown the deposition process until it eventually stops and only thinlayers of plated structures would be achievable. By having a sufficientamount of predeposited material that is being dissolved during theelectrochemical deposition reaction, the ion concentration remainsstable and thicker layers of plated structures can be achieved. Bychoosing the appropriate predeposited material (anode), seed layermaterial (cathode) and electrolyte, the desired dissolution anddeposition reaction can be achieved since they are thermodynamically andkinetically favorable in the chosen system. One example of anappropriate choice of electrochemical system is: having Cu aspredeposited material (anode), Cu as seed layer (cathode) and an acidiccopper sulfate bath as an electrolyte. In some cases, the depositionreaction does not have to be corresponding to the dissolution reactionexactly. As long as the dissolution rate of the predeposited material islarger than zero, the depletion of ion concentration in the electrolytewill be slower which means that it will take longer time before thereaction stops and hence thicker layers can be plated. For instance, thedissolution rate can be 90-100% of the deposition rate. In this example,the ion concentration of material being deposited will decrease slowly,but in some aspects a desired plated thickness can be achieved beforethe concentration becomes too low.

In all embodiments, the insulating pattern layer can be patterned inorder to compensate for topography with different heights and shapes byrepeating said lithography and/or etching steps and thereby creatingmultiple layers of cavities that can compensate for multiple layers oftopography on a substrate. The compensating cavities do not need to beexactly adapted to the topography 30 but may be arranged to be larger sothat the topography may be included inside the cavities with somemargin.

In some embodiments, said master electrodes that comprise an insulatingpattern layer with multiple layers of cavities can be used for formingmultiple ECPR plated structure layers in one single process step; saidstructure layer being defined by said multiple layers of cavities in theinsulating pattern layer.

In some embodiments, the master electrode is arranged using methods thatresults in very uniform height distribution of ECPR etched or platedstructure layers. However, in some other embodiment, at least someportion of the carrier and/or conducting electrode layer can be alteredin the cavities of an insulating pattern layer in order to give anon-uniform pattern in a portion of said structure layer. In oneembodiment, the carrier 1 of a master electrode 8 can have a recess inat least one cavity of an insulating pattern layer 7; said recess beingcoated on the walls with a conducting electrode layer 4; and apredeposited anode material 28 is arranged onto said conductingelectrode layer, as illustrated in FIG. 21( a). During ECPR plating on asubstrate 17 inside said cavities with said recesses, the areas locatedcloser to the walls of the insulating pattern layer 7 will achieve ahigher current density (plating rate) resulting in a larger height ofthe ECPR plated structures 24, as illustrated in FIG. 21( b).

In another embodiment, the carrier 1 and the conducting electrode layer4 exert a protruding structure in at least one cavity of an insulatingpattern layer 7; and a predeposited anode material 28 is arranged ontosaid conducting electrode layer, as illustrated in FIG. 22( a). DuringECPR plating on a substrate 17 inside said cavities with protrudingstructures, the areas on the substrate located closer to the protrudingstructure will achieve a higher current density (plating rate) resultingin a larger height of the ECPR plated structures 24, as illustrated inFIG. 22( b). In some case, the embodiments for creating structure layerswith a non-uniform height such as in FIG. 21( b) and FIG. 22( b) can beused for applications such as interlocking bump structures, solder ballplacement foundations or mechanical alignment structures/fiducials.

Herein above, several method steps have been described in differentcombinations and constellations. However, it is emphasized that othercombinations may be performed as occur to a skilled person reading thisspecification, and such combinations are within the scope of the presentinvention. Moreover, the different steps can be modified or alteredstill within the scope of the invention. The invention is only limitedby the appended patent claims.

1-244. (canceled)
 245. A master electrode for forming an electrochemicalcell with a substrate, comprising: a carrier at least partly of at leastone layer of a conducting and/or semi-conducting material; an insulatingpattern layer at least partly of at least one layer of an insulatingmaterial and arranged substantially at a front surface of said carrier;wherein said carrier comprises: a disc of at least one layer of aninsulating material, which is possibly transparent; a conductingelectrode layer of at least one layer of an electrode forming materialand covering at least a part of a front surface of the disc; a via layerof at least one layer of a conducting material and being in electricalcontact with said electrode layer.
 246. The master electrode of claim245, further comprising: a connection layer being in electric contactwith said via layer and electrode layer, wherein said connection layercomprises at least one layer of a conducting material covering at leasta portion of a backside surface of the disc.
 247. The master electrodeof claim 245, wherein said carrier is made from at least one layer of aconducting and/or semi-conducting material and is provided with aconducting electrode layer of a electrode forming, conducting materialin cavities of said insulating pattern layer.
 248. The master electrodeof claim 245, further comprising contacts means for engaging a substratesurface when the electrode is applied to said substrate for formingelectrical contact with said substrate surface.
 249. The masterelectrode of claim 248, wherein said contact means is arranged at theperipheral surface of the carrier outside said insulating material. 250.The master electrode of claim 245, wherein the disc is made from anelastic and/or flexible material.
 251. The master electrode of claim245, wherein an anode material is predeposited in cavities of theinsulating pattern layer in contact with said conducting electrodelayer.
 252. The master electrode of claim 245, wherein an adhesion layeris applied onto at least some parts of the carrier prior to applyingsaid conducting electrode layer; wherein said adhesion layer iscomprised of one or more materials that increase the adhesion of theconducting electrode layer to said carrier.
 253. The master electrode ofclaim 245, wherein an adhesion layer is arranged onto at least someparts of said carrier prior to arranging said insulating pattern layer;wherein said adhesion layer comprises at least one layer of materialthat improves the adhesion properties between the insulating patternlayer and the carrier.
 254. The master electrode of claim 245, furthercomprising an etch-stop layer, which is applied prior to applying saidinsulating pattern layer.
 255. The master electrode of claim 245,wherein the insulating pattern layer comprises one or more layers of atleast one material having properties such that the side-walls of thecavities of the insulating pattern layer are hydrophilic and the top ofthe insulating pattern layer is hydrophobic.
 256. The master electrodeof claim 245, wherein said insulating pattern layer is comprised of atleast one layer of a flexible material, or of at least one layer ofrigid material and at least one layer of a flexible material.
 257. Themaster electrode of claim 256, wherein said at least one layer offlexible materials is arranged on top of said at least one layer ofrigid material.
 258. The master electrode of claim 245, wherein saidcarrier or disc has a circular shape or a rectangular shape.
 259. Themaster electrode of claim 245, wherein the carrier or disc is providedwith recesses in the same region as recesses of the insulating patternlayer, said recesses of the carrier or disc having a conductingelectrode layer.
 260. The master electrode of claim 245, wherein saidinsulating pattern layer is provided by bonding and patterning abond-layer of an insulating material onto said carrier.
 261. The masterelectrode of claim 245, wherein the carrier or disc is provided withconnection sites as recesses or holes that allow for an externalelectrical connection to a substrate.
 262. The master electrode of claim261, wherein said carrier or disc is provided with at least one recessor hole in or near the perimeter.
 263. The master electrode of claim245, further comprising an electrical seed layer connection of aconducting, electrode forming material and being arranged in at leastsome parts between recesses on top of said insulating pattern layer,wherein said electrical seed layer connection is electrically isolatedby an insulating material from the conducting or semiconductingmaterials of the carrier, disc, conducting electrode layer, orconnection layer.
 264. The master electrode of claim 263, wherein saidelectrical seed layer connection is provided as a layer around the edgeof the carrier or disc.
 265. The master electrode of claim 263, whereindifferent portions of said electrical seed layer connection are providedwith connection areas at the back-side of the carrier and through thecarrier.
 266. The master electrode of claim 245, further comprisingalignment marks for aligning said master electrode to a substrate, saidalignment marks comprising structures or cavities in a layer on thefront side and/or back side of the master electrode.
 267. The masterelectrode of claim 245, wherein said carrier and the conductingelectrode layer include a protruding structure extending in at least onecavity of an insulating pattern layer, and a predeposited anode materialis arranged onto said conducting electrode layer.
 268. A method offorming a master electrode, comprising: providing a insulating dischaving a front surface and a back surface and of an insulating material;forming a connection via in said insulating disc of a conductingmaterial; forming an electrode layer of a conducting material on atleast a part of the front surface, said electrode layer being inelectrical connection with said via; and forming an insulating patternlayer comprising at least one cavity on said electrode layer.
 269. Themethod of claim 268, wherein the insulating material is applied with amethod selected from the group comprising: thermo-oxidation,Plasma-Enhanced-Chemical-Vapor Deposition (PECVD), Physical VaporDeposition (PVD), Chemical-Vapor-Deposition (CVD), electricalanodization, Atomic-Layer-Deposition (ALD), spin-coating, spray-coating,roller-coating, powder-coating, adhesive taping, pyrolysis, bonding, andcombinations thereof.
 270. The method of claim 268, further comprisingperforming a planarization step on said carrier.
 271. The method ofclaim 268, wherein said conducting electrode layer is applied withmethods selected from the group comprising: ALD,Metallorganic-Chemical-Vapor-Deposition (MOCVD), PVD, CVD, sputtering,electroless deposition, immersion deposition, electrodeposition,electro-grafting, chemical grafting, and combinations thereof.
 272. Themethod of claim 268, wherein said conducting electrode layer is treatedby thermal methods selected from the group comprising: annealing,rapid-thermal-annealing (RTA), furnace heating, hot-plate heating, andcombinations thereof.
 273. The method of claim 268, wherein saidconducting electrode layer is formed by applying several layers of atleast one material and by treating at least one layer by said thermalmethods before applying a next layer.
 274. The method of claims 268,wherein an adhesion layer is arranged onto at least some parts of saidcarrier prior to arranging said insulating pattern layer; wherein saidadhesion layer comprises at least one layer of material that improvesthe adhesion properties between the insulating pattern layer and thecarrier, wherein said adhesion layer is applied using deposition methodsselected from the group comprising: electrodeposition, spin-coating,spray-coating, dip-coating, and Molecular-Vapor-Deposition (MVD), ALD,MOCVD, CVD, PVD, sputtering, electroless deposition, immersiondeposition, electrografting, chemical grafting and combinations thereof.275. The method of claim 268, wherein a planarization step is performedon the arranged insulating pattern layer, wherein said planarizationstep is performed by a etching and/or polishing methods selected fromthe group comprising: chemical-mechanical-polishing (CMP), lapping,contact planarization (CP) and/or dry etching methods, and combinationsthereof.
 276. The method of claim 268, wherein said recesses in saidinsulating pattern layer are formed by using lithography, etchingmethods, and/or mechanical abrasive methods.
 277. The method of claim276, wherein said etching methods comprise arranging a patternedetch-mask onto at least some areas of said insulating pattern layer,said areas being protected from etching, wherein said patternedetch-mask is produced by lithography and/or etching methods, whereinsaid etch-mask is comprised of a polymer resist used in saidlithographical methods or a hard-mask.
 278. The method of claim 277,wherein said etch-mask comprises at least one structure layer forming insaid at least one electrochemical cell formed by a further masterelectrode.
 279. The method of claim 268, further comprising: using adamascene process to create the cavities of said insulating patternlayer, said damascene process involving applying a sacrificial patternlayer, having recesses, onto the carrier; applying an insulatingmaterial so that it cover said sacrificial pattern layer and fills upthe recesses of the sacrificial pattern; planarizing said insulatingmaterial until the sacrificial pattern layer is uncovered; and removingsaid sacrificial pattern layer whereby an insulating pattern layer isformed, wherein said sacrificial pattern is arranged by applying amaterial which is patterned by lithography, plating, and/or etchingmethods, or said sacrificial pattern layer comprises at least onestructure layer being formed in an electrochemical cell with a furthermaster electrode.
 280. The method of claim 268, further comprisingcoating a release layer onto at least some parts of the insulatingpattern layer.
 281. The method claim 268, further comprising treating atleast some surfaces of said insulating pattern layer with thermaltreatment, oxygen/nitrogen/argon plasma treatment, surface conversionfor anti-sticking (SURCAS), strong oxidizing agents, or combinationsthereof.
 282. The method of claim 268, further comprising: forming theinsulating pattern layer with lithographical and/or etching methods;creating cavities reaching down to the carrier or conducting electrode;patterning the insulating pattern layer once more in at least someareas; and creating cavities that compensate for topography on thesubstrate but do not reach the carrier or conducting electrode layer.283. The method of claim 268, wherein said insulating pattern layer ispatterned by repeating lithography and/or etching steps to createmultiple levels of cavities so as to compensate for multiple levels oftopography of different heights and shapes on a substrate.